This message is from the T13 list server.
On Thu, 11 Apr 2002 17:18:00 -0600, Pat LaVarre wrote: >This message is from the T13 list server. >I wonder if hosts ever write x04 SRST to >x3F6 DeviceControl without first terminating Dma? We must be careful here... To the ATA/ATAPI device there is only one host (the thing on the other side of the cable). But inside that host (and I'm using x86/PCI here) during DMA commands you could consider the host as actually two hosts: one host is the x86 and the other is the DMA engine. The DMA engine is a slave to the x86 and the device. It only runs when the x86 says to run, it only transfers data when the device wants to transfer data. And if the x86 says "I need to do this PIO operation now" then the DMA engine must stop the DMA data burst and allow the PIO operation. So it is not required that the x86 stop the DMA engine before writing the SRST bit. Might be a good idea but not required. >> a device executing a DMA data transfer command >> should have status of BSY=1 until the command is completed. >Is this required or only recommended by the Ansi texts? BSY=1 -and- BSY=0:DRQ=1 are both allowed. Neither is recommended. Neither is discouraged. Yes, I did say a device should have BSY=1 but that was just to make the point that the device registers are most likely not available for reading during DMA commands. And please don't forget that devices that do have BSY=0:DRQ=1 status may toggle between that status and BSY=1 status in an unpredicatable manner. So even if a host sees BSY=0:DRQ=1 by the time the host tries to read a register the status may have changed to BSY=1 status. >To my knowledge, how Ata/pi hosts & devices actually do mostly work isn't >written down with much precision - not at the bus analyser level, as opposed >to the digital scope level. I would say the reset and command protocol state diagrams in ATA/ATAPI-5 and -6 are fairly detailed and don't leave a lot to the imagination! Be aware that there is an error in (I think) the PACKET DMA device side state diagram. (If I remember correctly) This is fixed in the ATA/ATAPI-5 Errata document and in ATA/ATAPI-6. >What I'm hearing here more specifically is that one easily observable >distinction among Usb/AtapiUDma bridges is how promptly the bridge reports Usb >bCSWStatus = x02 PhaseError when the host & the device do disagree over which >direction to copy data. The bridge is an ATA/ATAPI host... There should NEVER be a command for which the bridge and the device disagree. The bridge must be a properly implemented ATA/ATAPI host and therefore it knows the data direction and data transfer size for EVERY command. >I haven't yet heard specifically how the bridge folk accomplish this. This is what makes bridge designs so much fun! *** Hale Landis *** www.ata-atapi.com ***
