This message is from the T13 list server.
On Mon, 15 Apr 2002 20:04:19 -0700, McGrath, Jim wrote: >This message is from the T13 list server. >My assertion is that there is no industry standard that prevents the PIO >access while under DMA. Individual chip set vendors all have their own >rules for handling things, but there is no industry consensus. There basically isn't any published documentation about how PCI bus ATA host adapters work is there? Look at all the issues that the reviews of the proposal T13 Host Adapter Standard document has found. (What? You mean a host adapter really has to do that?) But I'll repeat here what I said in a previous email plus some... The ATA interface has two operating modes: PIO, when DMACK- is not asserted by the host, -and- DMA, when DMACK- is asserted by the host. The biggest difference in these modes is that when DMACK- is asserted by the host the address signals CSx- and DAx are not used. And when DMACK- is asserted either the host is generating "I/O R/W" cycles (a MW DMA data burst) -or- many of the interface signals have a different meaning (a Ultra DMA data burst). Bottom line is that while DMACK- is asserted by the host it is not possible to perform a PIO I/O R/W cycle on the ATA interface. So what happens if a x86 does attempt an I/O R/W (an IN or OUT instruction) to an ATA device while the ATA host and device have the ATA interface in DMA mode? There is no way for the a PCI bus device, such as a PCI bus ATA host adapter, to tell the x86 "sorry but your I/O cycle is illegal now, go away". The ATA host adapter can tell the x86 to "go away" for awhile, and the ATA DMA burst can be terminated, then when the x86 comes back to retry the IN or OUT instruction, it can be done on the ATA interface. It can be done because the ATA host adapter terminated the DMA burst and returned the ATA interface to PIO mode. This is what all PCI bus ATA host adapters I have seen do. And 'no', I have never seen a single word of documentation about this. Now to continue... As I pointed out before, an ATA or ATAPI device executing a DMA data transfer command should have status of BSY=1 (or maybe BSY=0 DRQ=1, doesn't matter). If the host software does read the device status during this time it will see that the device is executing a command. And we know that reading any register of a device with BSY=1 is a special case: the device returns the contents of the status register. So wny do PCI bus ATA host adapters terminate a DMA data burst when the host does a I/O read of any ATA register? Good question... They don't need to... All the host adapter needs to do is return 0x80 data for the PCI bus I/O read and let the DMA burst on the ATA interface continue. But an I/O write to a ATA register should require the host adapter to terminate the DMA burst because the host might be trying to write 08H into the command register or write SRST=1. Yes, absolutely, I agree that in the case of a I/O write the host should shutdown the DMA engine before executing the OUT instruction to the ATA register, but this has never been a documented requirement -and- a PCI bus ATA host adapter has no way to enforce this anyway, it has no choice but to allow the x86 OUT instruction to function as expected. *** Hale Landis *** www.ata-atapi.com ***
