This message is from the T13 list server.
On Mon, 15 Apr 2002 18:17:14 -0500, Wolford, Jeff wrote: >This message is from the T13 list server. >Jim, >I do not agree with your statement at all that the hardware >is responsible to terminate the current DMA. If the host side controller hardware is not required to terminate the current DMA burst so that a x86 IN or OUT instruction can execute, then what does the host controller hardware do with the I/O R/W cycle on the PCI bus, for example, the PCI bus I/O read cycle that is the direct result of the x86 executing an IN instruction? The answer in all host controllers to date is this: Because there is no way to tell the x86 "sorry but that instruction just isn't legal now", host controllers terminate the current DMA burst on the ATA interface so that the I/O cycle to read the ATA Status register can happen. >DEFINITION: >It is only valid to access a device while the Host controller >is in active DMA mode, not while the ATA bus is in >active DMA mode (DREQ and DMACK active). >Does EVERYONE agree with that statement ? No, because I don't understand what you are trying to say... If you are trying to say that while the host controllers DMA engine is "active" the host shall not attempt to access the attached ATA device(s) then I would disagree that this was or is a requirement on the host. >It is determining this DREQ or DMACK (one or both being inactive) >state that is difficult for software to figure out BEFORE >it accesses the drive in PIO. Yes. That is why PCI bus ATA host adapters do what they do... Terminate the DMA burst and let the x86 IN or OUT instruction execute. >Under the first case, I agree the proper thing to be done >is disable the BM active bit in the host controller BEFORE the PIO Yes, and I agree if the host is trying to stop the current command, such as when the host wants to write SRST=1. But a host that doesn't use interrupts, aka a "polling host" that T13 has not outlawed, must be able to just read the ATA Status any time, even when the host DMA engine is active and even if there is a DMA burst in progress. Unless we want to change this in the new T13 host adapter standard? That would be changing host hardware functions that go back to the ISA bus DMA engines that are copied in current PCI bus ATA DMA engines. Wonder how much host software that would break? *** Hale Landis *** www.ata-atapi.com ***
