This message is from the T13 list server.
> you really have to run
> at the slowest cycle time
> regardless of the mode capability.
Anybody know if this is what Microsoft does,
or is this just a theoretical argument and a Bios
convention?
The spec doesn't trumpet this limitation, does it?
> master has to be online
> for all register accesses
Why the Master any more than the Slave?
They both have to watch for DEV and SRST
and ExecuteDeviceDiagnostic writes. There's
nothing that the Master alone has to watch for,
is there?
> numbers in excess of 300
Once upon a time I heard of Intel motherboards
that would cycle x1F0 Data reads at 300ns no matter
what you asked for, unless the last x1F7 Command
write was something other than xA0 Packet.
A device qualified under such conditions might
conservatively report that its qualified read time
was 300ns. I don't actually know of a device that
did so, but I'd be curious to know if one existed.
Curiously, lazily yours, Pat LaVarre
-----Original Message-----
From: Curtis Stevens [mailto:[EMAIL PROTECTED]]
Sent: Mon 10/7/2002 11:37 AM
To: [EMAIL PROTECTED]
Cc:
Subject: RE: [t13] Master and Slave speed
This message is from the T13 list server.
Pat & Co.
I have observed slower drives failing when a faster drive is the
slave. At the time I reached the conclusion that because the master has to
be online for all register accesses, even when the slave is currently
selected, it can get hung because of the faster access speeds. I observed
this behavior for both normal register access and PIO data transfers.
The issue also goes a bit deeper than PIO modes. Some drives
reported support for both PIO 2 and PIO 4, but when you looked at their
cycle times in the ID DEVICE data you found numbers in excess of 300ns; not
the usual 180 or 120... This means that although both drives may report
Mode 4 capability, you still must run at the slower speed. In this case you
were really running closer to Mode 1...
So, the answer to the question is that you really have to run at the
slowest cycle time regardless of the mode capability.
-----------------------
Curtis E. Stevens
Pacific Digital Corp.
2052 Alton Parkway
Irvine, CA 92606
Phone (949) 477-5713
Fax (949) 252-9397
E-Mail: [EMAIL PROTECTED]
WEB: www.PacificDigital.com
Never take life seriously... after all, nobody ever gets out alive!
-----Original Message-----
From: Pat LaVarre [mailto:[EMAIL PROTECTED]]
Sent: Monday, October 07, 2002 9:23 AM
To: [EMAIL PROTECTED]
Subject: RE: [t13] Master and Slave speed
This message is from the T13 list server.
> when DMACK is asserted by the host
> side, the address signals are "disabled" and not used.
Do the public specs carefully require DMACK to be
asserted with enough setup for a merely PIO 0 device
to know to ignore the address signals before the host
begins using them? And on the other end, do the specs
require the address signals to go quiet early enough
before DMACK is deasserted?
Curiously, lazily yours. Pat LaVarre
....
