This message is from the T13 list server. (B (B (BMr. Landis, (B (BThank you very much for the quick response. (B (B> No one. Those signals are normally pulled high by the host side of (B> the interface. (B (BIf this is the case, I can safely assume, the upper side of (Bthe data bus can be left released during register reads. (B (BInitially, I thought of this, too, but the standard only (Bspecified pull down on DD7. That was when I began to question (Bof the state of the DD15-8 pin during register reads. (B (BBut when you say, "normally", are you implying also that is (B"normally, but no always" ? (B (B> ...<snip>... During any IOR- cycle the device drives the (B> DDx signals, ...<snip>... (B> ...<snip>... (B> ...<snip>... During IOR- cycles (B> the device could drive all 16 DDx signals but the host would ignore (B> DD8-DD15. (B (BAre you saying, "device CAN" drive the DD8-15 during register reads, (Bbut "host should NEVER" drive the DD8-15 during IOR- cycles, and (B"host CAN" drive the DD8-15 during DIOW- cycles but "device should (BNEVER" drive DD8-15 during register writes ? (B (BMy understanding of the "usage" of DD8-15 are same as you. (B (BThanks. (B (BOn Thu, 09 Sep 2004 17:16:36 -0600 (B"Hale Landis" <[EMAIL PROTECTED]> wrote: (B (B> >This message is from the T13 list server. (B> >I have a question on Parallel ATA/ATAPI register reads. (B> >Who should be driving the upper 8 bit of the data (B> >port, DD[15:8], during register reads ? (B> >The host or the device ? (B> (B> No one. Those signals are normally pulled high by the host side of (B> the interface. During Command and Control Block register reads and (B> during reads of the Data register while the device is in 8-bit PIO (B> data transfer mode the DD8-DD15 signals are not driven by either side (B> of the interface. (B> (B> >Wrong understanding of this leads to bus conflict (B> >between the host and the device during register reads. (B> (B> No, should never happen. During any IOR- cycle the device drives the (B> DDx signals, during IOW- cycles the host drives the DDx signals. (B> During IOW- cycles the host could drive all 16 DDx signals but for (B> most IOW- cycles the device will ignore DD8-DD15. During IOR- cycles (B> the device could drive all 16 DDx signals but the host would ignore (B> DD8-DD15. (B> (B> The ONLY TIME DD8-DD15 are used is during commands that use PIO data (B> transfers AND the device is not in 8-bit data tranfer mode AND the (B> device has status of BSY=0 DRQ=1 AND the host is reading or writing (B> the device's Data register. (B> (B> See the IOR-/IOW- response tables in ATA/ATAPI-6. (B> (B> >I have read the ATA/ATAPI-7 document, but, could not (B> >find a sentence specific enough. Maybe, I have to (B> >look at older documents. (B> (B> If you are working on Parallel ATA (PATA) DO NOT USE ATA/ATAPI-7 - (B> USE ATA/ATAPI-6. (B> (B> Hale (B> (B> (B> *** Hale Landis *** www.ata-atapi.com *** (B> (B> (B (B------------------------------------------------- (BSony Corporation, (BSemiconductor Solutions Network Company (BSoC Solution Center $BBh([EMAIL PROTECTED](B1$BIt(B2$B2](B (BTel. +81-3-6834-5252 / Fax. +81-3-6834-5256 (BTel. 9-30-4-5252 / Fax. 9-30-4-5256 (Ext) (BTadashi Nakamura ([EMAIL PROTECTED])
