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Hi, I have a question on Parallel ATA/ATAPI register reads. Who should be driving the upper 8 bit of the data port, DD[15:8], during register reads ? The host or the device ? Wrong understanding of this leads to bus conflict between the host and the device during register reads. I have read the ATA/ATAPI-7 document, but, could not find a sentence specific enough. Maybe, I have to look at older documents. ------------------------------------------------- Sony Corporation Tadashi Nakamura
