This message is from the T13 list server.
On Fri, 10 Sep 2004 09:21:40 +0900, [EMAIL PROTECTED] wrote: >This message is from the T13 list server. >If this is the case, I can safely assume, the upper side of >the data bus can be left released during register reads. It would not make much sense for the host to drive the DDx signals during a IOR- cycle (just as it would not make much sense for the device to drive the DDx signals during a IOW- signal). >[...] but the standard only >specified pull down on DD7. That was when I began to question >of the state of the DD15-8 pin during register reads. >But when you say, "normally", are you implying also that is >"normally, but no always" ? Many systems, such as x86 based PC systems, pull the ATA DDx signals high, except DD7 that should be pulled low. But I see no reason why a system could not pull all of the DDx signals low. Except for the "termination" requirements of UltraDMA, I don't see that ATA/ATAPI-x specifies any pull up/down for any DDx signal other than DD7. >Are you saying, "device CAN" drive the DD8-15 during register reads, It could... Except for "valid 16-bit reads of the Data register (see below)" the host would never be looking at the DD8-DD15 signals therefore the host would never know what the device was or was not doing to the state of the DD8-DD15 signals. The same can be said for register writes... The host could drive the DD8-DD15 signals during register writes, but again, except for "valid 16-bit writes of the Data register (see below)" the drive would never be looking at the DD8-DD15 signals and therefore the drive would never know what the host was or was not doing to the state of the DD8-DD15 signals. NOTE: Definition of a valid 16-bit read/write of the Data register: The current command must be a PIO data tranfer command, the device must have status of BSY=0 DRQ=1 and the device must NOT be in 8-bit PIO data transfer mode (see the SET FEATURES FR=01H and FR=81H commands). Hale *** Hale Landis *** www.ata-atapi.com ***
