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Dear all, On page 175 of ATA/ATAPI-6, clause 8.28.5.2 says that the I/O bit shall be set to one indicating the transfer is to the host at bus release condition for READ DMA QUEUED EXT command. However, for READ DMA QUEUED, WRITE DMA QUEUED and WRITE DMA QUEUED EXT commands, the I/O bits are all required to be zero for bus release condition. I think that the text should be corrected as "I/O bit shall be cleared to zero" from normal outputs of bus release condition in clause 8.28.5.2 on page 175 of ATA/ATAPI-6. Does anyone give me correction or confirmation? Thank you! Best regards, Kepler
