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kepler wrote:
This message is from the T13 list server. On page 175 of ATA/ATAPI-6, clause 8.28.5.2 says that the I/O bit shall be set to one indicating the transfer is to the host at bus release condition for READ DMA QUEUED EXT command. However, for READ DMA QUEUED, WRITE DMA QUEUED and WRITE DMA QUEUED EXT commands, the I/O bits are all required to be zero for bus release condition.
Looks like a cut/paste typo to me.
I think that the text should be corrected as "I/O bit shall be cleared to zero" from normal outputs of bus release condition in clause 8.28.5.2 on page 175 of ATA/ATAPI-6.
Yes. And the same 'error' is in ATA/ATAPI-7. Also see the WRITE DMA QUEUED EXT command descriptions in both ATA/ATAPI-6 and in ATA/ATAPI-7... These also have an 'incorrect' description for the IO and CD bits at Bus Release.
Does anyone give me correction or confirmation? Thank you!
See the READ/WRITE DMA QUEUED commands - except for the difference of LBA28 or LBA48 the commands are the same as READ/WRITE DMA QUEUED EXT.
Hale -- ++ Hale Landis ++ [EMAIL PROTECTED] ++
