Jason, Robi,
I suspect that this problem is one that many of us have run into
before. I am assuming that your planes are probably polygon pours, if they
are then they are the real root of the problem being made up of so many
individual drawn entities. Probably several of them are GND nets of one
variation or another.
By the way, you don't mention whether you're using P98, P99 or
P99SE, I assume P99SE because of the thread title but I just found out today
that one other was posting to this thread when his comments applied to P98.
The problem seems to have been worst in P98.
If these planes are on power nets then it is suggested that you do
the following. In the Protel Explorer window select "Browse PCB" & "Nets"
for viewing in the slection window. Select your nets that include these
large power polygons and click the edit button, this brings up the Net
properties window. In the net properties window click "Hide". Repeat this
for each of the polygon nets and your delays should virtually disappear. The
only ramification of this operation is that your ratsnest for those nets
will not be displayed. You could also do this by double-clicking the
ratsnests but they can be difficult to select that way.
Second tip, always use the largest track sizes for polygon pours
that you possibly can. This reduces the number of elements making up the
polygons. Sometimes you may want to split the polygons because one area
could use large tracks while another needs fine tracks just in one area to
get through small tight areas.
Third tip, set your polygon grid to 0mils, this will perfectly align
the track segments edge to edge without any overlap and again reduce the
number of elements.
Been there, done that and have lived pretty much happily ever after since.
Hope this helps, it sure saved my hair retention.
Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com
> -----Original Message-----
> From: Jason Morgan [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, June 27, 2001 5:48 AM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] Speed problem with Protel 99SE in PCB editor !
>
>
> I would expect this to be true if you had complicated DRC
> rules, the ONLY
> rule we have is 'Whole Board min gap 8mil'
>
> I didn't explain the whole story, there is a definite problem
> with slowness
> in large designs,
> possibly caused by polygons. We even have polygon re-pour
> off and poly
> layers hidden.
>
> Premier will be getting a copy of the database soon so that
> they can suggest
> how to
> fix it.
>
> J.
>
>
>
> -----Original Message-----
> From: robi artwork [mailto:[EMAIL PROTECTED]]
> Sent: 27 June 2001 12:22
> To: Protel EDA Forum
> Subject: Re: [PEDA] Speed problem with Protel 99SE in PCB editor !
>
>
> To my knowledge - all it is, is the DRC, analyzing all your
> nets on board,
> every time you touch a dam thing!
> good practice - save and re-boot the system!!!
> Although, a slow system will effect the speed of handling
> components within
> the pcb editor, much more important are all your DRC-Definitions.
> Once you've poured a certain polygon you don't realy need the
> DRC-definition for it , anymore - unless you need to repour it.
> Therefor - disable, or even delete all DRC-Definitions you
> don't need at
> present.
> A bit more complicated but effective way of doing things like that -
> get rid of part of your netlist - reload the netlist, and
> work within the
> area you realy working in. - that is what I do for all
> supply-pins, on most
> of my Multilayer boards, after the placement is done.
> The moral of the story - please watch your DRC-Definitions as
> they are
> causing the major delay, while working
> Cheers
> Robi
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