Alfred Perlstein wrote:
> * Terry Lambert <[EMAIL PROTECTED]> [020331 00:05] wrote:
> > Michael Smith wrote:
> > > > What's the basis of the assumption that the I/O range is
> > > > unsupported in the first place, and why isn't it true for this
> > > > bridge chip, if it's a valid assumption for others?
> > >
> > > The information was provided in the debugging output and code that Alfred
> > > supplied in earlier messages. The short answer is "programmer error".
> > >
> > > You're walking into another conversation with insufficient context. 8)
> > Hey, I'll always sit still for someone willing to give me context...
> > 8-).
> > I was thinking it would be easier to get enough info to Alfred,
> > and let the patch pop out there. 8-) 8-).
> Issue is that there's something wonky with the PCI code such that
> it doesn't realize that the bus hanging off of a bus wants another
> memory range outside the PCI device's range. I wonder if there
> should be a flag to allow this? Some sort of escape mechanism?
> I need sleep. :)
Yeah, you do. I fully understood _that_ context; I think Mike
was talking about other context. It's pretty clear to me that
ranges ought to be per bridge chipset, rather than global... I
thought that that was what the option was working around: that
they were not.
The option might as well have "DO_NOT_USE_THIS_MAGIC_OPTION_"
as a prefix on it, the way it was being discussed. If that's
the case, then something is broken with the bridge handling
We all await your patch, since you have hardware to demonstrate
the problem and the fix... 8-) 8-) 8-).
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