Add the A840 CLX domain table and the IFF/PCLX limits table to the catalog. With the HFI plumbing in place, this enables the Current Limit Extension (CLX) feature on Adreno 840.
Signed-off-by: Akhil P Oommen <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 550ff3a9b82e..c503912a61c7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -2108,6 +2108,90 @@ static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist); +static const struct a6xx_hfi_clx_table_v2_cmd a840_clx_tbl = { + .version = (2 << 16) | 1, + .domain = { + /* GX DOMAIN */ + { + .data = CLX_DATA(60, 5, 1, 1), + .clxt = 0, + .clxh = 0, + .urg_mode = 1, + .lkg_en = 0, + .curr_budget = 100, + }, + /* MXG DOMAIN */ + { + .data = CLX_DATA(60, 1, 1, 1), + .clxt = 0, + .clxh = 0, + .urg_mode = 1, + .lkg_en = 0, + .curr_budget = 50, + }, + }, +}; + +struct a6xx_hfi_limits_tbl a840_limits_tbl[] = { + { + .feature_id = GMU_MIT_IFF, + .domain = GMU_GX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 12, + .mit_time = 5, + .curr_limit = 6000, + }, + }, + { + .feature_id = GMU_MIT_IFF, + .domain = GMU_MX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 9, + .mit_time = 2000, + .curr_limit = 6000, + }, + }, + { + .feature_id = GMU_MIT_PCLX, + .domain = GMU_GX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 1, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 7, + .mit_time = 3, + .curr_limit = 30000, + }, + }, + { + .feature_id = GMU_MIT_PCLX, + .domain = GMU_MX_DOMAIN, + .feature_rev = 0, + .cfg = { + .enable = 0, + .msg_path = 0, + .lkg_en = 0, + .mode = 0, + .sid = 7, + .mit_time = 3, + .curr_limit = 6000, + }, + }, +}; +DECLARE_ADRENO_LIMITS_TABLE(a840_limits); + static const struct adreno_info a8xx_gpus[] = { { .chip_ids = ADRENO_CHIP_IDS(0x44070001), @@ -2185,6 +2269,8 @@ static const struct adreno_info a8xx_gpus[] = { }, { /* sentinel */ }, }, + .clx_tbl = &a840_clx_tbl, + .limits_tbl = &a840_limits, }, .preempt_record_size = 19708 * SZ_1K, .speedbins = ADRENO_SPEEDBINS( -- 2.51.0
