On 5/15/26 10:07 PM, Akhil P Oommen wrote:
> Add support for Current Limit Extension (CLX) feature found on a few A8x
> GPUs. This feature is required to limit the peak current consumption to
> avoid HW spec violation on GX/MX rails.
>
> Add the necessary HFI interface support to pass the recommended CLX and
> IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed
> from the catalog entries.
>
> Signed-off-by: Akhil P Oommen <[email protected]>
> ---
[...]
> +static int a6xx_hfi_enable_clx(struct a6xx_gmu *gmu)
> +{
> + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
> + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> + const struct a6xx_info *info = adreno_gpu->info->a6xx;
> + struct a6xx_hfi_clx_table_v2_cmd cmd = { 0 };
> + int ret;
> +
> + if (!info->clx_tbl)
> + return 0;
> +
> + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_CLX, 1, 0);
> + if (ret) {
> + DRM_DEV_ERROR(gmu->dev, "Unable to enable CLX (%d)\n", ret);
> + return ret;
> + }
> +
> + memcpy(&cmd, info->clx_tbl, sizeof(cmd));
You're not adjusting anything (unlike the other function), so you can just pass
info->clx_tbl below
> +
> + ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CLX_TBL, &cmd, sizeof(cmd),
> NULL, 0);
> + if (ret) {
> + DRM_DEV_ERROR(gmu->dev, "Unable to send CLX table (%d)\n", ret);
> + return ret;
> + }
Konrad
