>Isn't nop often used in branching? Huh ? Nop is the "No Operation" instruction. x86 isn't RISC!!! >just iding until a hardware clock runs out we don't >want it to just be sitting there eating up cpu cycles >that could be used elsewhere--so why not trap "nop" >and thus allow the clock cycles to be put to good use >while redirecting any wait states into a virtual >hardware timer inside of the monitor? You're confused with HLT, here. However, using NOP as a proof-as-concept test has my approval, Kevin :-P -- Ramon
- Re: Scan-before-execute and I&D TLB technique success... Ulrich Weigand
- Re: Scan-before-execute and I&D TLB technique su... Kevin P. Lawton
- Re: Scan-before-execute and I&D TLB technique su... Jens Nerche
- Re: Scan-before-execute and I&D TLB techniqu... Kevin P. Lawton
- Re: Scan-before-execute and I&D TLB tech... Jens Nerche
- Re: Scan-before-execute and I&D TLB ... Kevin P. Lawton
- Re: Scan-before-execute and I&D... Jens Nerche
- Re: Scan-before-execute and I&D TLB technique success... Ramon van Handel
- Re: Scan-before-execute and I&D TLB technique su... Kevin P. Lawton
- Re: Scan-before-execute and I&D TLB technique success... Drew Northup
- Re: Scan-before-execute and I&D TLB technique success... Ramon van Handel
- Re: Scan-before-execute and I&D TLB technique su... Eider Oliveira
- Re: Scan-before-execute and I&D TLB techniqu... Ramon van Handel
- Re: Scan-before-execute and I&D TLB technique success... Drew Northup
- Re: Scan-before-execute and I&D TLB technique su... Kevin P. Lawton
