> Testing with the k10 (phenom-II) cpu in powersave mode (800 MHz) showed
> that the encoding required about <3% and decoding <6% of the 800 MHz.
>
> That is small enough that it just might fit into a Cortex-M4F, though
> the radio encoding may then require its own M4 or dsp.
>
> -JimC

A few comments/questions,

I tend to agree that a fixed pt implementation may not needed for a single 
chip solution now that chips like the Cortex M4F are starting to take hold.

One question is how much code/table/ram space is needed?  A quick gander 
seems to show some large codebook tables that may be the show stopper. 
Currently single chip micros are at best 1 or 2Mbytes of flash and even less 
ram.

Having played around with the M4F I think processing power is probably not 
an issue if one does a little optimizing.  I've ported the CuteSDR receiver 
code to an STM32F4 running 168MHz and it uses <50% cpu including the LWIP 
network stack and a full duplex implementation of the Speex codec.  Maybe 
apples and oranges but does show a lot of promise for doing DSP on simple 
uC.

Key optimizations are to use the single precision float math versions (cosf 
vs cos ) etc.  May not make a big difference on a big x86 but is essential 
for processors with single precision FPUs.  Other functions where full 
precision is not needed can further be optimized using some fast versions 
such as http://code.google.com/p/fastapprox/    ARM also provides a free arm 
optimised DSP source code library( CMSIS ) for basic dsp operations such as 
FFT,FIRs etc.

If the memory management stuff(malloc etc.) can be MACRO'd so can be 
replaced and the core codec2 code is not intertwined with other big OS 
library calls then there may be a chance for a single chip implementation. 
A low power(as in DC power) part is essential for codec2 to be used in 
portable battery applications.

Just the ramblings from a Neanderthal HW guy who runs away from any 
processor/OS with a memory management unit. :)

Moe, ae4jy




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