https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125339
Bug ID: 125339
Summary: Volatile memory access sequences on aarch64/ARM64 may
be compiled to post/pre increment instructions which
do not affect ESR_EL{1,2,3}
Product: gcc
Version: 16.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: leon.a at serenityos dot org
Target Milestone: ---
On virtualized systems HW emulation is done through page faults, and on ARM64
the hypervisor depends on the Exception Syndrome Register to contain the wanted
physical address.
On ARM the pre-/post-increment memory instruction do not affect this register
properly, forcing to hypervisors to either throw an error or attempt software
emulation, which most do not do.
For MMIO accesses C and C++ suggest using the `volatile` specifier, which
should
force compilers to emit correctly sized ordered accesses, and imo also emit
code that works in all HW situations (as in virtualized environments)
A similar bug is present LLVM[1], on which initially we thought that GCC did
avoid post/pre increment with volatile specifiers, as seen in this godbolt
example:
<https://godbolt.org/z/WqjrGKzEY>
But as it turns out in simpler situations GCC still chooses to emit
post/pre increment instructions:
<https://godbolt.org/z/9n5sjdW6W>
as found by nikic
Is this intentional and should this be addressed in any way
and is there any easy workaround for the projects relying on volatile for MMIO
accesses
[1]: LLVM issue <https://github.com/llvm/llvm-project/issues/173014>
