[Bug rtl-optimization/125339] Volatile memory access sequences on aarch64/ARM64 may be compiled to post/pre increment instructions which do not affect ESR_EL{1,2,3}

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125339

--- Comment #2 from Drea Pinski <pinskia at gcc dot gnu.org> ---
The easiest workaround is for all accesses do:

   asm("":"+r"(x));

After the load/store for the address.

I am not 100% sure if it is expected. GCC had tried in the past NOT to optimize
volatile accesses. But it looks like this one has worked this way since at
least GCC 5.