[Bug rtl-optimization/125339] Volatile memory access sequences on aarch64/ARM64 may be compiled to post/pre increment instructions which do not affect ESR_EL{1,2,3}

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125339

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
but it's the address that's optimized, not the access ...