https://gcc.gnu.org/g:df7625c3af004a81c13d54bb8810e03932eeb59a
commit r14-9846-gdf7625c3af004a81c13d54bb8810e03932eeb59a
Author: Thomas Schwinge <tschwi...@baylibre.com>
Date: Sat Feb 24 00:29:14 2024 +0100
GCN: '--param=gcn-preferred-vectorization-factor=[default,32,64]'
..., and specify '--param=gcn-preferred-vectorization-factor=64' for
'gcc.target/gcn/[...]' test cases with 'scan-assembler' directives that
are specific to 64-lane vectors. This resolves regressions introduced
in commit 6dedafe166cc02ae87b6a0699ad61ce3ffc46803
"amdgcn: Prefer V32 on RDNA devices".
gcc/
* config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor):
New.
* config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it.
* doc/invoke.texi (Optimize Options): Document it.
gcc/testsuite/
* gcc.target/gcn/cond_fmaxnm_1.c: Specify
'--param=gcn-preferred-vectorization-factor=64'.
* gcc.target/gcn/cond_fmaxnm_2.c: Likewise.
* gcc.target/gcn/cond_fmaxnm_3.c: Likewise.
* gcc.target/gcn/cond_fmaxnm_4.c: Likewise.
* gcc.target/gcn/cond_fmaxnm_5.c: Likewise.
* gcc.target/gcn/cond_fmaxnm_6.c: Likewise.
* gcc.target/gcn/cond_fmaxnm_7.c: Likewise.
* gcc.target/gcn/cond_fmaxnm_8.c: Likewise.
* gcc.target/gcn/cond_fminnm_1.c: Likewise.
* gcc.target/gcn/cond_fminnm_2.c: Likewise.
* gcc.target/gcn/cond_fminnm_3.c: Likewise.
* gcc.target/gcn/cond_fminnm_4.c: Likewise.
* gcc.target/gcn/cond_fminnm_5.c: Likewise.
* gcc.target/gcn/cond_fminnm_6.c: Likewise.
* gcc.target/gcn/cond_fminnm_7.c: Likewise.
* gcc.target/gcn/cond_fminnm_8.c: Likewise.
* gcc.target/gcn/cond_shift_3.c: Likewise.
* gcc.target/gcn/cond_shift_4.c: Likewise.
* gcc.target/gcn/cond_shift_8.c: Likewise.
* gcc.target/gcn/cond_shift_9.c: Likewise.
* gcc.target/gcn/cond_smax_1.c: Likewise.
* gcc.target/gcn/cond_smin_1.c: Likewise.
* gcc.target/gcn/cond_umax_1.c: Likewise.
* gcc.target/gcn/cond_umin_1.c: Likewise.
* gcc.target/gcn/simd-math-1.c: Likewise.
* gcc.target/gcn/simd-math-5-char.c: Likewise.
* gcc.target/gcn/simd-math-5-long.c: Likewise.
* gcc.target/gcn/simd-math-5-short.c: Likewise.
* gcc.target/gcn/simd-math-5.c: Likewise.
* gcc.target/gcn/smax_1.c: Likewise.
* gcc.target/gcn/smin_1.c: Likewise.
* gcc.target/gcn/umax_1.c: Likewise.
* gcc.target/gcn/umin_1.c: Likewise.
Diff:
---
gcc/config/gcn/gcn.cc | 14 +++++++++++++-
gcc/config/gcn/gcn.opt | 16 ++++++++++++++++
gcc/doc/invoke.texi | 8 ++++++++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_shift_3.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_shift_4.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_shift_8.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_shift_9.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_smax_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_smin_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_umax_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/cond_umin_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/simd-math-1.c | 3 ++-
gcc/testsuite/gcc.target/gcn/simd-math-5-char.c | 3 +++
gcc/testsuite/gcc.target/gcn/simd-math-5-long.c | 3 +++
gcc/testsuite/gcc.target/gcn/simd-math-5-short.c | 3 +++
gcc/testsuite/gcc.target/gcn/simd-math-5.c | 3 +++
gcc/testsuite/gcc.target/gcn/smax_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/smin_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/umax_1.c | 2 ++
gcc/testsuite/gcc.target/gcn/umin_1.c | 2 ++
36 files changed, 107 insertions(+), 2 deletions(-)
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 700e554855e..9f91d4f9ebd 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -5231,6 +5231,14 @@ gcn_vector_mode_supported_p (machine_mode mode)
static machine_mode
gcn_vectorize_preferred_simd_mode (scalar_mode mode)
{
+ bool v32;
+ if (gcn_preferred_vectorization_factor == 32)
+ v32 = true;
+ else if (gcn_preferred_vectorization_factor == 64)
+ v32 = false;
+ else if (gcn_preferred_vectorization_factor != -1)
+ gcc_unreachable ();
+ else if (TARGET_RDNA2_PLUS)
/* RDNA devices have 32-lane vectors with limited support for 64-bit vectors
(in particular, permute operations are only available for cases that don't
span the 32-lane boundary).
@@ -5238,7 +5246,11 @@ gcn_vectorize_preferred_simd_mode (scalar_mode mode)
From the RDNA3 manual: "Hardware may choose to skip either half if the
EXEC mask for that half is all zeros...". This means that preferring
32-lanes is a good stop-gap until we have proper wave32 support. */
- if (TARGET_RDNA2_PLUS)
+ v32 = true;
+ else
+ v32 = false;
+
+ if (v32)
switch (mode)
{
case E_QImode:
diff --git a/gcc/config/gcn/gcn.opt b/gcc/config/gcn/gcn.opt
index 1067b45f294..42bb5f75a42 100644
--- a/gcc/config/gcn/gcn.opt
+++ b/gcc/config/gcn/gcn.opt
@@ -116,3 +116,19 @@ Compile for devices requiring XNACK enabled. Default
\"any\" if USM is supported
msram-ecc=
Target RejectNegative Joined ToLower Enum(hsaco_attr_type) Var(flag_sram_ecc)
Init(HSACO_ATTR_ANY)
Compile for devices with the SRAM ECC feature enabled, or not. Default \"any\".
+
+-param=gcn-preferred-vectorization-factor=
+Target Joined Enum(gcn_preferred_vectorization_factor)
Var(gcn_preferred_vectorization_factor) Init(-1) Param
+--param=gcn-preferred-vectorization-factor=[default,32,64] Preferred
vectorization factor.
+
+Enum
+Name(gcn_preferred_vectorization_factor) Type(int)
+
+EnumValue
+Enum(gcn_preferred_vectorization_factor) String(default) Value(-1)
+
+EnumValue
+Enum(gcn_preferred_vectorization_factor) String(32) Value(32)
+
+EnumValue
+Enum(gcn_preferred_vectorization_factor) String(64) Value(64)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f5f5d83f817..0b1230b7bc3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17017,6 +17017,14 @@ loop. The default value is four.
@end table
+The following choices of @var{name} are available on GCN targets:
+
+@table @gcctabopt
+@item gcn-preferred-vectorization-factor
+Preferred vectorization factor: @samp{default}, @samp{32}, @samp{64}.
+
+@end table
+
The following choices of @var{name} are available on i386 and x86_64 targets:
@table @gcctabopt
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
index 17c49bdc518..29e77064bc5 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
index 406df48962a..f781ca2c013 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
index 45b8b7883ba..5da33ac2726 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
index 416aea89e6e..263db35dd49 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
index a4d7ab991de..6bfc2b9627f 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include "cond_fmaxnm_1.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
index 6c64a01bcbb..8ea52725cbe 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include "cond_fmaxnm_2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
index bdb3f2f99ef..97f8cf57ee3 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include "cond_fmaxnm_3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
index c11633b5236..9de89790a12 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include "cond_fmaxnm_4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
index bb456887568..7068e8c4f54 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_1.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
index 502f8987494..d8ee9446e38 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
index 2ea1eb2ec2c..59bbc5610ce 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
index 3673ecafc2d..07e6aae8919 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
index ac98941a373..84ab917043d 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_1.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
index 7f4dba0d314..a1525d91b33 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
index 5faf0c5cc59..bb5e0f24d5b 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
index 89d93ac596a..c090377c0e1 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#define FN(X) __builtin_fmin##X
#include "cond_fmaxnm_4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
index 983386c1464..1181384a495 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
index c610363d9df..ea2110d0a6f 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
index 0749e2e5e53..9942a2e167c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
index 61aba27504e..663192f97e7 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
index 342b5e827d2..212091a15df 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
index ad8b583448b..714aab2f7f7 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
index 389228f9e4a..9018b006817 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
index 65759d695ad..64d0a5eb350 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-1.c
b/gcc/testsuite/gcc.target/gcn/simd-math-1.c
index 6868ccb2c54..abd6a932a01 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-1.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-1.c
@@ -2,7 +2,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -fno-math-errno -mstack-size=3000000
-fdump-tree-vect" } */
-
+/* The 'scan-tree-dump' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#undef PRINT_RESULT
#define VERBOSE 0
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
index 2321c8390c6..e3521ce7ca3 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
@@ -1,3 +1,6 @@
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
#define TYPE char
#include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
index 37b6cef691e..96a9fd3e734 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
@@ -1,3 +1,6 @@
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
#define TYPE long
#include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
index 84cdc9b5fdd..c0bff40380a 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
@@ -1,3 +1,6 @@
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
#define TYPE short
#include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5.c
b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
index bc181b45e1b..b5c5dc9f288 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
@@ -1,6 +1,9 @@
/* Test that the auto-vectorizer uses the libgcc vectorized division and
modulus functions. */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+
/* Setting it this way ensures the run tests use the same flag as the
compile tests. */
#pragma GCC optimize("O2")
diff --git a/gcc/testsuite/gcc.target/gcn/smax_1.c
b/gcc/testsuite/gcc.target/gcn/smax_1.c
index 46c21f73132..eec050caf71 100644
--- a/gcc/testsuite/gcc.target/gcn/smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/smax_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/smin_1.c
b/gcc/testsuite/gcc.target/gcn/smin_1.c
index 8d6edfaa3d1..8aa8cbb9db8 100644
--- a/gcc/testsuite/gcc.target/gcn/smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/smin_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/umax_1.c
b/gcc/testsuite/gcc.target/gcn/umax_1.c
index dc4b9842d9a..934bf9a4a7c 100644
--- a/gcc/testsuite/gcc.target/gcn/umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/umax_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/gcn/umin_1.c
b/gcc/testsuite/gcc.target/gcn/umin_1.c
index d07f7ec083b..44343bd44cf 100644
--- a/gcc/testsuite/gcc.target/gcn/umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/umin_1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -ftree-vectorize -dp" } */
+/* The 'scan-assembler' directives are specific to 64-lane vectors.
+ { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
#include <stdint.h>
