https://gcc.gnu.org/g:819056304acea25b44313f402a5d9d51bf49d4cf
commit 819056304acea25b44313f402a5d9d51bf49d4cf
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri May 24 13:20:47 2024 -0400
Add -mintspr.
2024-05-24 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -mintspr.
* config/rs6000/rs6000.md (mov<mode>_internal): Add support for
moving
QI/HImode to/from SPRs back.
* config/rs6000/rs6000.opt (-mintspr): New switch.
Diff:
---
gcc/config/rs6000/rs6000.cc | 6 +++++-
gcc/config/rs6000/rs6000.md | 17 ++++++++++-------
gcc/config/rs6000/rs6000.opt | 4 ++++
3 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f72c62f4e5f..fa330c2a4b1 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1952,7 +1952,11 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
case LR_REGNO:
case CTR_REGNO:
case TAR_REGNO:
- return (!orig_complex_p && mode == Pmode);
+ return (!orig_complex_p
+ && (mode == Pmode
+ || (TARGET_INTSPR
+ && SCALAR_INT_MODE_P (mode)
+ && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)));
default:
break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d1ab06998c7..b5dc0719a88 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8064,16 +8064,16 @@
;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI
;; XXLOR load 0 load -1 VSPLTI* # MFVSRWZ
-;; MTVSRWZ
+;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
"=r, r, wa, m, ?Z, r,
wa, wa, wa, v, ?v, r,
- wa")
+ wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
"r, m, ?Z, r, wa, i,
wa, O, wM, wB, wS, wa,
- r"))]
+ r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode)"
"@
@@ -8089,19 +8089,22 @@
vspltis<wd> %0,%1
#
mfvsrwz %0,%x1
- mtvsrwz %x0,%1"
+ mtvsrwz %x0,%1
+ mf%1 %0
+ mt%0 %1
+ nop"
[(set_attr "type"
"*, load, fpload, store, fpstore, *,
vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr,
- mtvsr")
+ mtvsr, mfjmpr, mtjmpr, *")
(set_attr "length"
"*, *, *, *, *, *,
*, *, *, *, 8, *,
- *")
+ *, *, *, *")
(set_attr "isa"
"*, *, p9v, *, p9v, *,
p9v, p9v, p9v, p9v, p9v, p9v,
- p9v")])
+ p9v, *, *, *")])
;; Here is how to move condition codes around. When we store CC data in
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 7f7a283bc99..bac74695f64 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,10 @@ mtar
Target Undocumented Mask(TAR) Var(rs6000_isa_flags)
Allow (do not allow) use the TAR register.
+mintspr
+Target Undocumented Var(TARGET_INTSPR) Init(0) Save
+Allow (do not allow) small integers in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
