https://gcc.gnu.org/g:d9181d77435b2037dfbdf7e1b54de8d3e2748beb
commit d9181d77435b2037dfbdf7e1b54de8d3e2748beb Author: Jeff Law <j...@ventanamicro.com> Date: Sun Jun 2 13:19:16 2024 -0600 Just the riscv bits from: commit a0d60660f2aae2d79685f73d568facb2397582d8 Author: Andrew Pinski <quic_apin...@quicinc.com> Date: Wed May 29 20:40:31 2024 -0700 Fix some opindex for some options [PR115022] While looking at the index I noticed that some options had `-` in the front for the index which is wrong. And then I noticed there was no index for `mcmodel=` for targets or had used `-mcmodel` incorrectly. This fixes both of those and regnerates the urls files see that `-mcmodel=` option now has an url associated with it. gcc/ChangeLog: PR target/115022 * doc/invoke.texi (fstrub=disable): Fix opindex. (minline-memops-threshold): Fix opindex. (mcmodel=): Add opindex and fix them. * common.opt.urls: Regenerate. * config/aarch64/aarch64.opt.urls: Regenerate. * config/bpf/bpf.opt.urls: Regenerate. * config/i386/i386.opt.urls: Regenerate. * config/loongarch/loongarch.opt.urls: Regenerate. * config/nds32/nds32-elf.opt.urls: Regenerate. * config/nds32/nds32-linux.opt.urls: Regenerate. * config/or1k/or1k.opt.urls: Regenerate. * config/riscv/riscv.opt.urls: Regenerate. * config/rs6000/aix64.opt.urls: Regenerate. * config/rs6000/linux64.opt.urls: Regenerate. * config/sparc/sparc.opt.urls: Regenerate. Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com> Diff: --- gcc/config/riscv/riscv.opt.urls | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls index e02ef3ee3dd..d87e9d5c9a8 100644 --- a/gcc/config/riscv/riscv.opt.urls +++ b/gcc/config/riscv/riscv.opt.urls @@ -41,7 +41,8 @@ UrlSuffix(gcc/RISC-V-Options.html#index-msave-restore) mshorten-memrefs UrlSuffix(gcc/RISC-V-Options.html#index-mshorten-memrefs) -; skipping UrlSuffix for 'mcmodel=' due to finding no URLs +mcmodel= +UrlSuffix(gcc/RISC-V-Options.html#index-mcmodel_003d-4) mstrict-align UrlSuffix(gcc/RISC-V-Options.html#index-mstrict-align-4)