The branch 'meissner/heads/work176-vpair' was updated to point to:
b9f77deab8b... Merge commit 'refs/users/meissner/heads/work176-vpair' of g
It previously pointed to:
217eac978ad... Add ChangeLog.vpair and update REVISION.
Diff:
Summary of changes (added commits):
-----------------------------------
b9f77de... Merge commit 'refs/users/meissner/heads/work176-vpair' of g
9adc2e6... Add ChangeLog.vpair and update REVISION.
248fc70... Merge commit 'refs/users/meissner/heads/work176' of git+ssh (*)
03ac745... Update ChangeLog.* (*)
aa65901... Add -mcpu=future tuning support. (*)
3031a7c... Add support for -mcpu=future (*)
df189b6... Update ChangeLog.* (*)
9e3ab51... Update tests to work with architecture flags changes. (*)
255d09d... Change TARGET_MODULO to TARGET_POWER9 (*)
2f2353e... Change TARGET_POPCNTD to TARGET_POWER7 (*)
daa12c0... Change TARGET_CMPB to TARGET_POWER6 (*)
9b740bf... Change TARGET_FPRND to TARGET_POWER5X (*)
d83a1cd... Change TARGET_POPCNTB to TARGET_POWER5 (*)
eeab600... Do not allow -mvsx to boost processor to power7. (*)
5825848... Use architecture flags for defining _ARCH_PWR macros. (*)
7a80d6a... Add rs6000 architecture masks. (*)
b04aa92... Add ChangeLog.meissner and REVISION. (*)
fceecc5... aarch64: Fix ls64 intrinsic availability (*)
4e1b617... aarch64: Fix memtag intrinsic availability (*)
32afbb6... aarch64: Fix tme intrinsic availability (*)
baf71ec... aarch64: Move check_required_extensions (*)
a4b39dc... aarch64: Refactor check_required_extensions (*)
8871489... Allow coarrays in select type. [PR46371, PR56496] (*)
9cbcf8d... gnat: fix lto-type-mismatch between C_Version_String and gn (*)
cc57224... aarch64: Reduce FP reassociation width for Neoverse V2 and (*)
6d8b9b7... testsuite: Prune warning about size of enums (*)
e57d3cc... rtl: Enable the use of rtx values with int and mode attribu (*)
71059d2... testsuite: Reduce cut-&-paste in scanltranstree.exp (*)
661acde... Fix ICE in recompute_tree_invariant_for_addr_expr, at tree. (*)
8d6c6fb... aarch64: Implement 16-byte vector mode const0 store by TImo (*)
7f62e71... AVX10.2 ymm rounding: Support vsqrtp{s,d,h} and vsubp{s,d,h (*)
1f86cf0... AVX10.2 ymm rounding: Support vscalefp{s,d,h} intrins (*)
9afa508... AVX10.2 ymm rounding: Support vreducep{s,d,h} and vrndscale (*)
90cc5b0... AVX10.2 ymm rounding: Support vmulp{s,d,h} and vrangep{s,d} (*)
cc8a759... AVX10.2 ymm rounding: Support v{max,min}p{s,d,h} intrins (*)
8d4f542... AVX10.2 ymm rounding: Support vgetexpp{s,d,h} and vgetmantp (*)
0983d40... AVX10.2 ymm rounding: Support vfnmsub{132,231,213}p{s,d,h} (*)
6f0aa7a... AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132,231, (*)
dd48acb... AVX10.2 ymm rounding: Support vfm{sub,subadd}{132,231,213}p (*)
cfbc94e... AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132,2 (*)
0683ca3... AVX10.2 ymm rounding: Support vfmadd{132,231,213}p{s,d,h} i (*)
95980b2... AVX10.2 ymm rounding: Support vfc{madd,mul}cph, vfixupimmp{ (*)
3d1b553... AVX10.2 ymm rounding: Support vcvt{,u}w2ph and vdivp{s,d,h} (*)
b275422... AVX10.2 ymm rounding: Support vcvttps2{,u}{dq,qq} and vcvtu (*)
493c509... AVX10.2 ymm rounding: Support vcvttph2{,u}{dq,qq,w} intrins (*)
6e231f8... AVX10.2 ymm rounding: Support vcvtqq2p{s,d,h} and vcvttpd2{ (*)
0f5a42d... AVX10.2 ymm rounding: Support vcvtps2{,u}{dq,qq} intrins (*)
b70bb94... AVX10.2 ymm rounding: Support vcvtph2{,u}w and vcvtps2p{d,h (*)
6f2eac5... AVX10.2 ymm rounding: Support vcvtph2p{s,d,sx} and vcvtph2{ (*)
508ac49... AVX10.2 ymm rounding: Support vcvtpd2{,u}{dq,qq} intrins (*)
85e874d... AVX10.2 ymm rounding: Support vcvtdq2p{s,h} and vcvtpd2p{s, (*)
e22e3af... AVX10.2 ymm rounding: Support vadd{s,d,h} and vcmp{s,d,h} i (*)
f11bc08... Daily bump. (*)
f10d2ee... [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc (*)
fc41263... libstdc++: Remove note from the GCC 4.0.1 days (*)
b9ac01d... doc: Tweak gm2 mailing list address (*)
cd2f394... PHIOPT: move factor_out_conditional_operation over to use g (*)
1cfe4a4... libgfortran: implement fpu-macppc for Darwin, support IEEE (*)
1ed1dd5... AVR: Tweak 16-bit addition with const that didn't get a LD_ (*)
22acd3c... AVR: ad target/116407 - Fix linker error "relocation trunca (*)
dfb2e8c... AVR: target/116407 - Fix linker error "relocation truncated (*)
3ae8794... forwprop: Also dce from added statements from gimple_simpli (*)
a183b25... RISC-V: Implement the quad and oct .SAT_TRUNC for scalar (*)
e8f31f4... RISC-V: Make sure high bits of usadd operands is clean for (*)
8d0efcf... RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3 (*)
6fbdbad... RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2 (*)
0555f65... Daily bump. (*)
61e179b... [committed] Avoid right shifting signed value on ext-dce.cc (*)
efcfd1d... t-rtems: add rv32imf architecture to the RTEMS multilib for (*)
abfc140... Adjust v850 rotate expander to allow more cases for V850E3V (*)
6d734ba... RISC-V: Fix ICE for vector single-width integer multiply-ad (*)
7aed8de... [RISC-V][PR target/116282] Stabilize pattern conditions (*)
3f51684... RISC-V: Bugfix for RVV rounding intrinsic ICE in function c (*)
06ae7bc... RISC-V: Bugfix incorrect operand for vwsll auto-vect (*)
54b228d... RISC-V: Add auto-vect pattern for vector rotate shift (*)
e68ab0f... libstdc++: Update references to gcc.gnu.org/onlinedocs (*)
2af5784... doc: Tweak PIM4 link (*)
16b92be... libstdc++: Tweak links to installation docs (*)
b9f0845... doc: Tweak link to gm2 list archive (*)
4065d16... AVR: target/116390 - Fix an avrtiny asm out template. (*)
04913bc... Update ChangeLog.* (*)
862273d... Add -mcpu=future tuning support. (*)
1a0f571... Add support for -mcpu=future (*)
bd41633... Update ChangeLog.* (*)
83888e7... Update tests to work with architecture flags changes. (*)
a11dcaf... RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116 (*)
1bef5eb... Change TARGET_MODULO to TARGET_POWER9 (*)
43359c8... Change TARGET_POPCNTD to TARGET_POWER7 (*)
4e6ae51... Change TARGET_CMPB to TARGET_POWER6 (*)
ea9055a... Change TARGET_FPRND to TARGET_POWER5X (*)
96a9f1f... Change TARGET_POPCNTB to TARGET_POWER5 (*)
b179980... Do not allow -mvsx to boost processor to power7. (*)
efc8619... Use architecture flags for defining _ARCH_PWR macros. (*)
a073d61... Add rs6000 architecture masks. (*)
3c9c93f... Daily bump. (*)
(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work176-vpair' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.
