[gcc r15-3704] i386: Add ssemov2, sseicvt2 for some load instructions that use memory on operand2

[Hu via Gcc-cvs]

https://gcc.gnu.org/g:1cf1bf7899985df31e1ebccb5d6f1ca762991dcf

commit r15-3704-g1cf1bf7899985df31e1ebccb5d6f1ca762991dcf
Author: Hu, Lin1 <lin1...@intel.com>
Date:   Wed Sep 11 10:10:40 2024 +0800

    i386: Add ssemov2, sseicvt2 for some load instructions that use memory on 
operand2
    
    The memory attr of some instructions should be 'load', but these are
    'none', currently.
    
    gcc/ChangeLog:
    
            * config/i386/i386.md: Add ssemov2, sseicvt2.
            * config/i386/sse.md (sse2_cvtsi2sd): Apply sseicvt2.
            (sse2_cvtsi2sdq<round_name>): Ditto.
            (vec_set<mode>_0): Apply ssemov2 for 4, 6.

Diff:
---
 gcc/config/i386/i386.md | 11 +++++++----
 gcc/config/i386/sse.md  |  6 ++++--
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c04415149490..9c2a0aa61126 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -539,10 +539,10 @@
    str,bitmanip,
    fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,
    fxch,fistp,fisttp,frndint,
-   sse,ssemov,sseadd,sseadd1,sseiadd,sseiadd1,
+   sse,ssemov,ssemov2,sseadd,sseadd1,sseiadd,sseiadd1,
    ssemul,sseimul,ssediv,sselog,sselog1,
    sseishft,sseishft1,ssecmp,ssecomi,
-   ssecvt,ssecvt1,sseicvt,sseins,
+   ssecvt,ssecvt1,sseicvt,sseicvt2,sseins,
    sseshuf,sseshuf1,ssemuladd,sse4arg,
    lwp,mskmov,msklog,
    mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
@@ -560,10 +560,10 @@
   (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,
                          fxch,fistp,fisttp,frndint")
           (const_string "i387")
-        (eq_attr "type" "sse,ssemov,sseadd,sseadd1,sseiadd,sseiadd1,
+        (eq_attr "type" "sse,ssemov,ssemov2,sseadd,sseadd1,sseiadd,sseiadd1,
                          ssemul,sseimul,ssediv,sselog,sselog1,
                          sseishft,sseishft1,ssecmp,ssecomi,
-                         ssecvt,ssecvt1,sseicvt,sseins,
+                         ssecvt,ssecvt1,sseicvt,sseicvt2,sseins,
                          sseshuf,sseshuf1,ssemuladd,sse4arg,mskmov")
           (const_string "sse")
         (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
@@ -858,6 +858,9 @@
                   mmx,mmxmov,mmxcmp,mmxcvt,mskmov,msklog")
              (match_operand 2 "memory_operand"))
           (const_string "load")
+        (and (eq_attr "type" "ssemov2,sseicvt2")
+             (match_operand 2 "memory_operand"))
+          (const_string "load")
         (and (eq_attr "type" "icmov,ssemuladd,sse4arg")
              (match_operand 3 "memory_operand"))
           (const_string "load")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1ae61182d0cc..ff4f33b7b637 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8876,7 +8876,7 @@
    cvtsi2sd{l}\t{%2, %0|%0, %2}
    vcvtsi2sd{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "type" "sseicvt")
+   (set_attr "type" "sseicvt2")
    (set_attr "athlon_decode" "double,direct,*")
    (set_attr "amdfam10_decode" "vector,double,*")
    (set_attr "bdver1_decode" "double,direct,*")
@@ -8898,7 +8898,7 @@
    cvtsi2sd{q}\t{%2, %0|%0, %2}
    vcvtsi2sd{q}\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
   [(set_attr "isa" "noavx,noavx,avx")
-   (set_attr "type" "sseicvt")
+   (set_attr "type" "sseicvt2")
    (set_attr "athlon_decode" "double,direct,*")
    (set_attr "amdfam10_decode" "vector,double,*")
    (set_attr "bdver1_decode" "double,direct,*")
@@ -11808,6 +11808,8 @@
              (const_string "imov")
            (eq_attr "alternative" "14")
              (const_string "fmov")
+           (eq_attr "alternative" "4,6")
+             (const_string "ssemov2")
           ]
           (const_string "ssemov")))
    (set (attr "addr")