[gcc r15-4461] AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0

[Tamar Christina via Gcc-cvs]

https://gcc.gnu.org/g:453d3d90c374d3bb329f1431b7dfb8d0510a88b9

commit r15-4461-g453d3d90c374d3bb329f1431b7dfb8d0510a88b9
Author: Tamar Christina <tamar.christ...@arm.com>
Date:   Fri Oct 18 09:44:15 2024 +0100

    AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0
    
    This patch changes SVE to use Adv. SIMD movi 0 to clear SVE registers when 
not
    in SVE streaming mode.  As the Neoverse Software Optimization guides 
indicate
    SVE mov #0 is not a zero cost move.
    
    When In streaming mode we continue to use SVE's mov to clear the registers.
    
    Tests have already been updated.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.cc (aarch64_output_sve_mov_immediate): Use
            fmov for SVE zeros.

Diff:
---
 gcc/config/aarch64/aarch64.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index e65b24e2ad6a..3ab550acc7cd 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -25516,8 +25516,11 @@ aarch64_output_sve_mov_immediate (rtx const_vector)
        }
     }
 
-  snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC,
-           element_char, INTVAL (info.u.mov.value));
+  if (info.u.mov.value == const0_rtx && TARGET_NON_STREAMING)
+    snprintf (templ, sizeof (templ), "movi\t%%d0, #0");
+  else
+    snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC,
+             element_char, INTVAL (info.u.mov.value));
   return templ;
 }