https://gcc.gnu.org/g:848be2528cd3731de39b8f7416112443ebfc1a6e
commit 848be2528cd3731de39b8f7416112443ebfc1a6e
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Nov 6 13:20:30 2024 -0500
Revert changes
Diff:
---
gcc/ChangeLog.meissner | 425 +-----------------------
gcc/config.gcc | 4 +-
gcc/config/rs6000/aix71.h | 1 -
gcc/config/rs6000/aix72.h | 1 -
gcc/config/rs6000/aix73.h | 1 -
gcc/config/rs6000/dfp.md | 2 +-
gcc/config/rs6000/driver-rs6000.cc | 2 -
gcc/config/rs6000/power10.md | 144 ++++----
gcc/config/rs6000/rs6000-arch.def | 49 ---
gcc/config/rs6000/rs6000-builtin.cc | 14 +-
gcc/config/rs6000/rs6000-c.cc | 29 +-
gcc/config/rs6000/rs6000-cpus.def | 11 +-
gcc/config/rs6000/rs6000-opts.h | 1 -
gcc/config/rs6000/rs6000-protos.h | 5 +-
gcc/config/rs6000/rs6000-string.cc | 4 +-
gcc/config/rs6000/rs6000-tables.opt | 11 +-
gcc/config/rs6000/rs6000.cc | 403 ++++++----------------
gcc/config/rs6000/rs6000.h | 82 ++---
gcc/config/rs6000/rs6000.md | 66 ++--
gcc/config/rs6000/rs6000.opt | 19 +-
gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 38 +--
gcc/testsuite/gcc.target/powerpc/pr115688.c | 3 +-
22 files changed, 297 insertions(+), 1018 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 77e940a625fb..a04bd0a46f88 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,417 +1,14 @@
-==================== Branch work182, patch #21 ====================
-
-Add -mcpu=future tuning support.
-
-This patch makes -mtune=future use the same tuning decision as -mtune=power11.
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/power10.md (all reservations): Add future as an
- alterntive to power10 and power11.
-
-==================== Branch work182, patch #20 ====================
-
-Add support for -mcpu=future
-
-This patch adds the support that can be used in developing GCC support for
-future PowerPC processors.
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
- * config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
- * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future.
- * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
- * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
- * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
- * config/rs6000/rs6000-arch.def: Add future cpu.
- * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
- -mcpu=future, define _ARCH_FUTURE.
- * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
- (future cpu): Define.
- * config/rs6000/rs6000-opts.h (enum processor_type): Add
- PROCESSOR_FUTURE.
- * config/rs6000/rs6000-tables.opt: Regenerate.
- * config/rs6000/rs6000.cc (power10_cost): Update comment.
- (get_arch_flags): Add support for future processor.
- (rs6000_option_override_internal): Likewise.
- (rs6000_machine_from_flags): Likewise.
- (rs6000_reassociation_width): Likewise.
- (rs6000_adjust_cost): Likewise.
- (rs6000_issue_rate): Likewise.
- (rs6000_sched_reorder): Likewise.
- (rs6000_sched_reorder2): Likewise.
- (rs6000_register_move_cost): Likewise.
- * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
- (TARGET_POWER11): New macro.
- * config/rs6000/rs6000.md (cpu attribute): Likewise.
-
-==================== Branch work182, patch #9 ====================
-
-Update tests to work with architecture flags changes.
-
-Two tests used -mvsx to raise the processor level to at least power7. These
-tests were rewritten to add cpu=power7 support.
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/testsuite/
-
- * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
- when we need to add VSX support. Add test for adding cpu=power7 no-vsx
- to generate only Altivec instructions.
- * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
- instructions.
-
-==================== Branch work182, patch #8 ====================
-
-Change TARGET_MODULO to TARGET_POWER9
-
-As part of the architecture flags patches, this patch changes the use of
-TARGET_MODULO to TARGET_POWER9. The modulo instructions were added in power9
(ISA
-3.0). Note, I did not change the uses of TARGET_MODULO where it was explicitly
-generating different code if the machine had a modulo instruction.
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
- TARGET_POWER9 instead of TARGET_MODULO.
- * config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
- (TARGET_EXTSWSLI): Likewise.
- (TARGET_MADDLD): Likewise.
- * config/rs6000/rs6000.md (enabled attribute): Likewise.
-
-==================== Branch work182, patch #7 ====================
-
-Change TARGET_POPCNTD to TARGET_POWER7
-
-As part of the architecture flags patches, this patch changes the use of
-TARGET_POPCNTD to TARGET_POWER7. The POPCNTD instruction was added in power7
-(ISA 2.06).
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
- TARGET_POWER7.
- * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
- Likewise.
- * config/rs6000/rs6000-string.cc (expand_block_compare_gpr): Likewise.
- * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
- Likewise.
- (rs6000_rtx_costs): Likewise.
- (rs6000_emit_popcount): Likewise.
- * config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
- (TARGET_LFIWZX): Likewise.
- (TARGET_FCFIDS): Likewise.
- (TARGET_FCFIDU): Likewise.
- (TARGET_FCFIDUS): Likewise.
- (TARGET_FCTIDUZ): Likewise.
- (TARGET_FCTIWUZ): Likewise.
- (CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
- * config/rs6000/rs6000.md (enabled attribute): Likewise.
- (ctz<mode>2): Likewise.
- (popcntd<mode>2): Likewise.
- (lrint<mode>si2): Likewise.
- (lrint<mode>si): Likewise.
- (lrint<mode>si_di): Likewise.
- (cmpmemsi): Likewise.
- (bpermd_<mode>"): Likewise.
- (addg6s): Likewise.
- (cdtbcd): Likewise.
- (cbcdtd): Likewise.
- (div<div_extend>_<mode>): Likewise.
-
-==================== Branch work182, patch #6 ====================
-
-Change TARGET_CMPB to TARGET_POWER6
-
-As part of the architecture flags patches, this patch changes the use of
-TARGET_FPRND to TARGET_POWER6. The CMPB instruction was added in power6 (ISA
-2.05).
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
- TARGET_POWER6 instead of TARGET_CMPB.
- * config/rs6000/rs6000.h (TARGET_FCFID): Merge tests for popcntb, cmpb,
- and popcntd into a single test for TARGET_POWER5.
- (TARGET_LFIWAX): Use TARGET_POWER6 instead of TARGET_CMPB.
- * config/rs6000/rs6000.md (enabled attribute): Likewise.
- (parity<mode>2_cmp): Likewise.
- (cmpb): Likewise.
- (copysign<mode>3): Likewise.
- (copysign<mode>3_fcpsgn): Likewise.
- (cmpstrnsi): Likewise.
- (cmpstrsi): Likewise.
-
-==================== Branch work182, patch #5 ====================
-
-Change TARGET_FPRND to TARGET_POWER5X
-
-As part of the architecture flags patches, this patch changes the use of
-TARGET_FPRND to TARGET_POWER5X. The FPRND instruction was added in power5+.
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (report_architecture_mismatch): Use
- TARGET_POWER5X instead of TARGET_FPRND.
- * config/rs6000/rs6000.md (fmod<mode>3): Use TARGET_POWER5X instead of
- TARGET_FPRND.
- (remainder<mode>3): Likewise.
- (fctiwuz_<mode>): Likewise.
- (btrunc<mode>2): Likewise.
- (ceil<mode>2): Likewise.
- (floor<mode>2): Likewise.
- (round<mode>): Likewise.
-
-==================== Branch work182, patch #4 ====================
-
-Change TARGET_POPCNTB to TARGET_POWER5
-
-As part of the architecture flags patches, this patch changes the use of
-TARGET_POPCNTB to TARGET_POWER5. The POPCNTB instruction was added in ISA 2.02
-(power5).
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
- TARGET_POWER5 instead of TARGET_POPCNTB.
- * config/rs6000/rs6000.h (TARGET_EXTRA_BUILTINS): Use TARGET_POWER5
- instead of TARGET_POPCNTB. Eliminate TARGET_CMPB and TARGET_POPCNTD
- tests since TARGET_POWER5 will always be true for those tests.
- (TARGET_FRE): Use TARGET_POWER5 instead of TARGET_POPCNTB.
- (TARGET_FRSQRTES): Likewise.
- * config/rs6000/rs6000.md (enabled attribute): Likewise.
- (popcount<mode>): Use TARGET_POWER5 instead of TARGET_POPCNTB. Drop
- test for TARGET_POPCNTD (i.e power7), since TARGET_POPCNTB will always
- be set if TARGET_POPCNTD is set.
- (popcntb<mode>2): Use TARGET_POWER5 instead of TARGET_POPCNTB.
- (parity<mode>2): Likewise.
- (parity<mode>2_cmpb): Remove TARGET_POPCNTB test, since it will always
- be true when TARGET_CMPB (i.e. power6) is set.
-
-
-==================== Branch work182, patch #3 ====================
-
-Do not allow -mvsx to boost processor to power7.
-
-This patch restructures the code so that -mvsx for example will not silently
-convert the processor to power7. The user must now use -mcpu=power7 or higher.
-This means if the user does -mvsx and the default processor does not have VSX
-support, it will be an error.
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
- Report an error if the user used an option such as -mvsx when the
- default processor would not allow the option.
- (rs6000_option_override_internal): Move some ISA checking code into
- report_architecture_mismatch.
-
-==================== Branch work182, patch #2 ====================
-
-Use architecture flags for defining _ARCH_PWR macros.
-
-For the newer architectures, this patch changes GCC to define the _ARCH_PWR<n>
-macros using the new architecture flags instead of relying on isa options like
--mpower10.
-
-The -mpower8-internal, -mpower10, and -mpower11 options were removed. The
--mpower11 option was removed completely, since it was just added in GCC 15.
The
-other two options were marked as WarnRemoved, and the various ISA bits were
-removed.
-
-TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
-instead of the ISA bits.
-
-There are other internal isa bits that aren't removed with this patch because
-the built-in function support uses those bits.
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
- use architecture flags instead of ISA flags for setting most of the
- _ARCH_PWR* macros.
- (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
- * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
- OPTION_MASK_POWER8.
- (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
- (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
- (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
- OPTION_MASK_POWER11.
- * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
- declaration.
- (rs6000_target_modify_macros_ptr): Likewise.
- * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
- (rs6000_option_override_internal): Use architecture flags instead of ISA
- flags.
- (rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no longer
- in the ISA flags.
- (rs6000_pragma_target_parse): Use architecture flags as well as ISA
- flags.
- * config/rs6000/rs6000.h (TARGET_POWER4): New macro.
- (TARGET_POWER5): Likewise.
- (TARGET_POWER5X): Likewise.
- (TARGET_POWER6): Likewise.
- (TARGET_POWER7): Likewise.
- (TARGET_POWER8): Likewise.
- (TARGET_POWER9): Likewise.
- (TARGET_POWER10): Likewise.
- (TARGET_POWER11): Likewise.
- * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
- (-mpower10): Likewise.
- (-mpower11): Likewise.
-
-==================== Branch work182, patch #1 ====================
-
-Add rs6000 architecture masks.
-
-This patch begins the journey to move architecture bits that are not user ISA
-options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The
-intention is to remove switches that are currently isa options, but the user
-should not be using this particular option. For example, we want users to use
--mcpu=power10 and not just -mpower10.
-
-This patch also changes the target_clones support to use an architecture mask
-instead of isa bits.
-
-This patch also switches the handling of .machine to use architecture masks if
-they exist (power4 through power11). All of the other PowerPCs will continue
to
-use the existing code for setting the .machine option.
-
-I have built both big endian and little endian bootstrap compilers and there
-were no regressions.
-
-In addition, I constructed a test case that used every archiecture define (like
-_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran
-this test for all supported combinations of -mcpu, big/little endian, and 32/64
-bit support. Every single instance generated exactly the same code with the
-patches installed compared to the compiler before installing the patches.
-
-Can I install this patch on the GCC 15 trunk?
-
-2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000-arch.def: New file.
- * config/rs6000/rs6000.cc (struct clone_map): Switch to using
- architecture masks instead of ISA masks.
- (rs6000_clone_map): Likewise.
- (rs6000_print_isa_options): Add an architecture flags argument, change
- all callers.
- (get_arch_flag): New function.
- (rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
- (rs6000_option_override_internal): Likewise.
- (rs6000_machine_from_flags): Switch to using architecture masks instead
- of ISA masks.
- (struct rs6000_arch_mask): New structure.
- (rs6000_arch_masks): New table of architecutre masks and names.
- (rs6000_function_specific_save): Save architecture flags.
- (rs6000_function_specific_restore): Restore architecture flags.
- (rs6000_function_specific_print): Update rs6000_print_isa_options calls.
- (rs6000_print_options_internal): Add architecture flags options.
- (rs6000_clone_priority): Switch to using architecture masks instead of
- ISA masks.
- (rs6000_can_inline_p): Don't allow inling if the callee requires a newer
- architecture than the caller.
- * config/rs6000/rs6000.h: Use rs6000-arch.def to create the architecture
- masks.
- * config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
- (x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.
+==================== Branch work182, patch #21 was reverted
====================
+==================== Branch work182, patch #20 was reverted
====================
+==================== Branch work182, patch #9 was reverted
====================
+==================== Branch work182, patch #8 was reverted
====================
+==================== Branch work182, patch #7 was reverted
====================
+==================== Branch work182, patch #6 was reverted
====================
+==================== Branch work182, patch #5 was reverted
====================
+==================== Branch work182, patch #4 was reverted
====================
+==================== Branch work182, patch #3 was reverted
====================
+==================== Branch work182, patch #2 was reverted
====================
+==================== Branch work182, patch #1 was reverted
====================
==================== Branch work182, baseline ====================
diff --git a/gcc/config.gcc b/gcc/config.gcc
index d552d01b4390..fd8482287228 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -539,7 +539,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5647,7 +5647,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
- "" | common | native | future \
+ "" | common | native \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 570ddcc451db..41037b3852d7 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 242ca94bd065..fe59f8319b48 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 2bd6b4bb3c4f..1318b0b3662d 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index b8189390d410..fa9d7dd45dd3 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POWER7"
+ "TARGET_DFP && TARGET_POPCNTD"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index c47e8b70c931..f4900724b98a 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -452,7 +452,6 @@ static const struct asm_name asm_names[] = {
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
{ "power11", "-mpwr11" },
- { "future", "-mfuture" },
{ "powerpc", "-mppc" },
{ "rs64", "-mppc" },
{ "603", "-m603" },
@@ -482,7 +481,6 @@ static const struct asm_name asm_names[] = {
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
{ "power11", "-mpower11" },
- { "future", "-mfuture" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index e42b057dc45b..2310c4603457 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10, Power11, and Future processors.
+;; Scheduling description for the IBM Power10 and Power11 processors.
;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-fused-load" 4
(and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-load-update" 4
(and (eq_attr "type" "load")
(eq_attr "update" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-fpload-update-double" 4
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-fpload-update-single" 7
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-vecload" 4
(and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
; lxvp
(define_insn_reservation "power10-vecload-pair" 4
(and (eq_attr "type" "vecload")
(eq_attr "size" "256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
(define_insn_reservation "power10-fused-store" 0
(and (eq_attr "type" "fused_store_store")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
(define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
; Update forms have 2 cycle latency for updated addr reg
(define_insn_reservation "power10-store-update" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "update" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
; stxvp
(define_insn_reservation "power10-vecstore-pair" 0
(and (eq_attr "type" "vecstore")
(eq_attr "size" "256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,stu0_power10+stu1_power10")
(define_insn_reservation "power10-larx" 4
(and (eq_attr "type" "load_l")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
; All load quad forms
(define_insn_reservation "power10-lq" 4
(and (eq_attr "type" "load,load_l")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-stcx" 0
(and (eq_attr "type" "store_c")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
; All store quad forms
(define_insn_reservation "power10-stq" 0
(and (eq_attr "type" "store,store_c")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,stu0_power10+stu1_power10")
(define_insn_reservation "power10-sync" 1
(and (eq_attr "type" "sync,isync")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
@@ -248,7 +248,7 @@
(define_insn_reservation "power10-alu" 2
(and (eq_attr "type" "add,exts,integer,logical,isel")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 4 cycle CR latency
(define_bypass 4 "power10-alu"
@@ -256,28 +256,28 @@
(define_insn_reservation "power10-fused_alu" 2
(and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; paddi
(define_insn_reservation "power10-paddi" 2
(and (eq_attr "type" "add")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; Rotate/shift (non-record form)
(define_insn_reservation "power10-rot" 2
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; Record form rotate/shift
(define_insn_reservation "power10-rot-compare" 3
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 5 cycle CR latency
(define_bypass 5 "power10-rot-compare"
@@ -285,7 +285,7 @@
(define_insn_reservation "power10-alu2" 3
(and (eq_attr "type" "cntlz,popcnt,trap")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 5 cycle CR latency
(define_bypass 5 "power10-alu2"
@@ -293,24 +293,24 @@
(define_insn_reservation "power10-cmp" 2
(and (eq_attr "type" "cmp")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; Treat 'two' and 'three' types as 2 or 3 way cracked
(define_insn_reservation "power10-two" 4
(and (eq_attr "type" "two")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-three" 6
(and (eq_attr "type" "three")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_all_power10,EXU_power10")
(define_insn_reservation "power10-mul" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 4 cycle MUL->MUL latency
(define_bypass 4 "power10-mul"
@@ -319,7 +319,7 @@
(define_insn_reservation "power10-mul-compare" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; 4 cycle MUL->MUL latency
(define_bypass 4 "power10-mul-compare"
@@ -331,13 +331,13 @@
(define_insn_reservation "power10-div" 12
(and (eq_attr "type" "div")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-div-compare" 12
(and (eq_attr "type" "div")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; 14 cycle CR latency
(define_bypass 14 "power10-div-compare"
@@ -345,34 +345,34 @@
(define_insn_reservation "power10-crlogical" 2
(and (eq_attr "type" "cr_logical")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfcrf" 2
(and (eq_attr "type" "mfcrf")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfcr" 3
(and (eq_attr "type" "mfcr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; Should differentiate between 1 cr field and > 1 since target of > 1 cr
; is cracked
(define_insn_reservation "power10-mtcr" 3
(and (eq_attr "type" "mtcr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mtjmpr" 3
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -380,126 +380,126 @@
(define_insn_reservation "power10-fpsimple" 3
(and (eq_attr "type" "fpsimple")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fp" 5
(and (eq_attr "type" "fp,dmul")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fpcompare" 3
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-sdiv" 22
(and (eq_attr "type" "sdiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-ddiv" 27
(and (eq_attr "type" "ddiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-sqrt" 26
(and (eq_attr "type" "ssqrt")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-dsqrt" 36
(and (eq_attr "type" "dsqrt")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vec-2cyc" 2
(and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fused-vec" 2
(and (eq_attr "type" "fused_vector")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-veccmp" 3
(and (eq_attr "type" "veccmp")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecsimple" 2
(and (eq_attr "type" "vecsimple")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecnormal" 5
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qp" 12
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "prefixed" "no")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecperm-compare" 3
(and (eq_attr "type" "vecperm")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-prefixed-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-veccomplex" 6
(and (eq_attr "type" "veccomplex")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecfdiv" 24
(and (eq_attr "type" "vecfdiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecdiv" 27
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qpdiv" 56
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qpmul" 24
(and (eq_attr "type" "qmul")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mtvsr" 2
(and (eq_attr "type" "mtvsr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfvsr" 2
(and (eq_attr "type" "mfvsr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -507,26 +507,26 @@
; Branch is 2 cycles, grouped with STU for issue
(define_insn_reservation "power10-branch" 2
(and (eq_attr "type" "jmpreg,branch")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
(define_insn_reservation "power10-fused-branch" 3
(and (eq_attr "type" "fused_mtbc")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
; Crypto
(define_insn_reservation "power10-crypto" 4
(and (eq_attr "type" "crypto")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; HTM
(define_insn_reservation "power10-htm" 2
(and (eq_attr "type" "htmsimple,htm")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -535,26 +535,26 @@
(define_insn_reservation "power10-dfp" 12
(and (eq_attr "type" "dfp")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-dfpq" 12
(and (eq_attr "type" "dfp")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; MMA
(define_insn_reservation "power10-mma" 9
(and (eq_attr "type" "mma")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_super_power10")
(define_insn_reservation "power10-prefixed-mma" 9
(and (eq_attr "type" "mma")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_super_power10")
; 4 cycle MMA->MMA latency
(define_bypass 4 "power10-mma,power10-prefixed-mma"
diff --git a/gcc/config/rs6000/rs6000-arch.def
b/gcc/config/rs6000/rs6000-arch.def
deleted file mode 100644
index d103c57867a1..000000000000
--- a/gcc/config/rs6000/rs6000-arch.def
+++ /dev/null
@@ -1,49 +0,0 @@
-/* IBM RS/6000 CPU architecture features by processor type.
- Copyright (C) 1991-2024 Free Software Foundation, Inc.
- Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-/* This file defines architecture features that are based on the -mcpu=<proc>
- option, and not on user options that can be turned on or off. The intention
- is for newer processors (power7 and above) to not add new ISA bits for the
- particular processor, but add these bits. Otherwise we have to add a bunch
- of hidden options, just so we have the proper ISA bits.
-
- For example, in the past we added -mpower8-internal, so that on power8,
- power9, and power10 would inherit the option, but we had to mark the option
- generate a warning if the user actually used it. These options have been
- moved from the ISA flags to the arch flags.
-
- To use this, define the macro ARCH_EXPAND which takes 2 arguments. The
- first argument is the processor name in upper case, and the second argument
- is a text name for the processor.
-
- The function get_arch_flags when passed a processor index number will set up
- the appropriate architecture flags based on the actual processor
- enumeration. */
-
-ARCH_EXPAND(POWER4, "power4")
-ARCH_EXPAND(POWER5, "power5")
-ARCH_EXPAND(POWER5X, "power5+")
-ARCH_EXPAND(POWER6, "power6")
-ARCH_EXPAND(POWER7, "power7")
-ARCH_EXPAND(POWER8, "power8")
-ARCH_EXPAND(POWER9, "power9")
-ARCH_EXPAND(POWER10, "power10")
-ARCH_EXPAND(POWER11, "power11")
-ARCH_EXPAND(FUTURE, "future")
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index b6093b3cb64c..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,23 +155,23 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_ALWAYS:
return true;
case ENB_P5:
- return TARGET_POWER5;
+ return TARGET_POPCNTB;
case ENB_P6:
- return TARGET_POWER6;
+ return TARGET_CMPB;
case ENB_P6_64:
- return TARGET_POWER6 && TARGET_POWERPC64;
+ return TARGET_CMPB && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POWER7;
+ return TARGET_POPCNTD;
case ENB_P7_64:
- return TARGET_POWER7 && TARGET_POWERPC64;
+ return TARGET_POPCNTD && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
- return TARGET_POWER9;
+ return TARGET_MODULO;
case ENB_P9_64:
- return TARGET_POWER9 && TARGET_POWERPC64;
+ return TARGET_MODULO && TARGET_POWERPC64;
case ENB_P9V:
return TARGET_P9_VECTOR;
case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 82826f96a8e7..04882c396bfe 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,8 +338,7 @@ rs6000_define_or_undefine_macro (bool define_p, const char
*name)
#pragma GCC target, we need to adjust the macros dynamically. */
void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
- HOST_WIDE_INT arch_flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
{
if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
fprintf (stderr,
@@ -412,7 +411,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags,
summary of the flags associated with particular cpu
definitions. */
- /* rs6000_isa_flags and rs6000_arch_flags based options. */
+ /* rs6000_isa_flags based options. */
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -420,28 +419,24 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags,
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
if ((flags & OPTION_MASK_POWERPC64) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
- if ((flags & OPTION_MASK_POWERPC64) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
- if ((arch_flags & ARCH_MASK_POWER4) != 0)
+ if ((flags & OPTION_MASK_MFCRF) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
- if ((arch_flags & ARCH_MASK_POWER5) != 0)
+ if ((flags & OPTION_MASK_POPCNTB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
- if ((arch_flags & ARCH_MASK_POWER5X) != 0)
+ if ((flags & OPTION_MASK_FPRND) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
- if ((arch_flags & ARCH_MASK_POWER6) != 0)
+ if ((flags & OPTION_MASK_CMPB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((arch_flags & ARCH_MASK_POWER7) != 0)
+ if ((flags & OPTION_MASK_POPCNTD) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
- if ((arch_flags & ARCH_MASK_POWER8) != 0)
+ if ((flags & OPTION_MASK_POWER8) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
- if ((arch_flags & ARCH_MASK_POWER9) != 0)
+ if ((flags & OPTION_MASK_MODULO) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
- if ((arch_flags & ARCH_MASK_POWER10) != 0)
+ if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
- if ((arch_flags & ARCH_MASK_POWER11) != 0)
+ if ((flags & OPTION_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
- if ((arch_flags & ARCH_MASK_FUTURE) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
@@ -610,7 +605,7 @@ void
rs6000_cpu_cpp_builtins (cpp_reader *pfile)
{
/* Define all of the common macros. */
- rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_arch_flags);
+ rs6000_target_modify_macros (true, rs6000_isa_flags);
if (TARGET_FRE)
builtin_define ("__RECIP__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index e73d9ef51f8d..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
+ | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
@@ -82,11 +83,11 @@
| OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
+ | OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
-#define POWER11_MASKS_SERVER ISA_3_1_MASKS_SERVER
-
-#define FUTURE_MASKS_SERVER POWER11_MASKS_SERVER
+#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
@@ -124,6 +125,8 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
+ | OPTION_MASK_POWER10 \
+ | OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
@@ -132,6 +135,7 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
+ | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
@@ -251,7 +255,6 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 |
ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
ISA_3_1_MASKS_SERVER)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
POWER11_MASKS_SERVER)
-RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
| MASK_POWERPC64)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index c25ddf92858c..88e357835a5c 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -63,7 +63,6 @@ enum processor_type
PROCESSOR_POWER9,
PROCESSOR_POWER10,
PROCESSOR_POWER11,
- PROCESSOR_FUTURE,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index da658cd5ab2e..b40557a85577 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -323,9 +323,8 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
extern bool rs6000_pragma_target_parse (tree, tree);
#endif
extern void rs6000_activate_target_options (tree new_tree);
-extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
-extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
- HOST_WIDE_INT);
+extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT);
+extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
#ifdef NO_DOLLAR_IN_LABEL
const char * rs6000_xcoff_strip_dollar (const char *);
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index 3674c4bd9847..55b4133b1a34 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes,
unsigned int base_align,
bool
expand_block_compare (rtx operands[])
{
- /* TARGET_POWER7 is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POWER7);
+ /* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
+ gcc_assert (TARGET_POPCNTD);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000-tables.opt
b/gcc/config/rs6000/rs6000-tables.opt
index fc187c641f8d..a5649fef1ece 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -189,17 +189,14 @@ EnumValue
Enum(rs6000_cpu_opt_value) String(power11) Value(53)
EnumValue
-Enum(rs6000_cpu_opt_value) String(future) Value(54)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
+Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
-
-EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
+Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index aa67e7256bb9..0bf8bae27f5d 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -252,17 +252,17 @@ enum {
/* Map compiler ISA bits into HWCAP names. */
struct clone_map {
- HOST_WIDE_INT arch_mask; /* rs6000_arch_mask. */
+ HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
const char *name; /* name to use in __builtin_cpu_supports. */
};
static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
- { 0, "" }, /* Default options. */
- { ARCH_MASK_POWER6, "arch_2_05" }, /* ISA 2.05 (power6). */
- { ARCH_MASK_POWER7, "arch_2_06" }, /* ISA 2.06 (power7). */
- { ARCH_MASK_POWER8, "arch_2_07" }, /* ISA 2.07 (power8). */
- { ARCH_MASK_POWER9, "arch_3_00" }, /* ISA 3.0 (power9). */
- { ARCH_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
+ { 0, "" }, /* Default options. */
+ { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
+ { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
+ { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
+ { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */
+ { OPTION_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
};
@@ -278,7 +278,7 @@ bool cpu_builtin_p = false;
/* Pointer to function (in rs6000-c.cc) that can define or undefine target
macros that have changed. Languages that don't support the preprocessor
don't link in rs6000-c.cc, so we can't call it directly. */
-void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
+void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
/* Simplfy register classes into simpler classifications. We assume
GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
@@ -1068,7 +1068,7 @@ struct processor_costs power9_cost = {
COSTS_N_INSNS (3), /* SF->DF convert */
};
-/* Instruction costs on Power10/Power11/future processors. */
+/* Instruction costs on Power10/Power11 processors. */
static const
struct processor_costs power10_cost = {
COSTS_N_INSNS (2), /* mulsi */
@@ -1171,9 +1171,8 @@ enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
enum reg_class)
const int INSN_NOT_AVAILABLE = -1;
static void rs6000_print_isa_options (FILE *, int, const char *,
- HOST_WIDE_INT, HOST_WIDE_INT);
+ HOST_WIDE_INT);
static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
-static void report_architecture_mismatch (void);
static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -1819,87 +1818,6 @@ rs6000_cpu_name_lookup (const char *name)
return -1;
}
-
-/* Map the processor into the arch bits that are set off of -mcpu=<xxx> instead
- of having an internal -m<foo> option. */
-
-static HOST_WIDE_INT
-get_arch_flags (int cpu_index)
-{
- HOST_WIDE_INT ret = 0;
-
- const HOST_WIDE_INT ARCH_COMBO_POWER4 = ARCH_MASK_POWER4;
- const HOST_WIDE_INT ARCH_COMBO_POWER5 = ARCH_MASK_POWER5 |
ARCH_COMBO_POWER4;
- const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X |
ARCH_COMBO_POWER5;
- const HOST_WIDE_INT ARCH_COMBO_POWER6 = ARCH_MASK_POWER6 |
ARCH_COMBO_POWER5X;
- const HOST_WIDE_INT ARCH_COMBO_POWER7 = ARCH_MASK_POWER7 |
ARCH_COMBO_POWER6;
- const HOST_WIDE_INT ARCH_COMBO_POWER8 = ARCH_MASK_POWER8 |
ARCH_COMBO_POWER7;
- const HOST_WIDE_INT ARCH_COMBO_POWER9 = ARCH_MASK_POWER9 |
ARCH_COMBO_POWER8;
- const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 |
ARCH_COMBO_POWER9;
- const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 |
ARCH_COMBO_POWER10;
- const HOST_WIDE_INT ARCH_COMBO_FUTURE = ARCH_MASK_FUTURE |
ARCH_COMBO_POWER11;
-
- if (cpu_index >= 0)
- switch (processor_target_table[cpu_index].processor)
- {
- case PROCESSOR_FUTURE:
- ret = ARCH_COMBO_FUTURE;
- break;
-
- case PROCESSOR_POWER11:
- ret = ARCH_COMBO_POWER11;
- break;
-
- case PROCESSOR_POWER10:
- ret = ARCH_COMBO_POWER10;
- break;
-
- case PROCESSOR_POWER9:
- ret = ARCH_COMBO_POWER9;
- break;
-
- case PROCESSOR_POWER8:
- ret = ARCH_COMBO_POWER8;
- break;
-
- case PROCESSOR_POWER7:
- ret = ARCH_COMBO_POWER7;
- break;
-
- case PROCESSOR_PPCA2:
- case PROCESSOR_POWER6:
- ret = ARCH_COMBO_POWER6;
- break;
-
- case PROCESSOR_POWER5:
- ret = ARCH_COMBO_POWER5;
- if (TARGET_FPRND)
- ret |= ARCH_MASK_POWER5X;
- break;
-
- case PROCESSOR_POWER4:
- ret = ARCH_COMBO_POWER4;
- break;
-
- default:
- /* For other processors, set the arch flags based on the ISA bits. */
- if (TARGET_MFCRF)
- ret |= ARCH_MASK_POWER4;
-
- if (TARGET_POPCNTB)
- ret |= ARCH_MASK_POWER5;
-
- if (TARGET_FPRND)
- ret |= ARCH_MASK_POWER5X;
-
- if (TARGET_CMPB)
- ret |= ARCH_MASK_POWER6;
- break;
- }
-
- return ret;
-}
-
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
@@ -2004,7 +1922,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POWER7 && mode == SImode)
+ if (TARGET_POPCNTD && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -2481,10 +2399,9 @@ rs6000_debug_reg_global (void)
const char *name = processor_target_table[rs6000_cpu_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_cpu_index].target_enable;
- HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_cpu_index);
sprintf (flags_buffer, "-mcpu=%s flags", name);
- rs6000_print_isa_options (stderr, 0, flags_buffer, flags, arch_flags);
+ rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
@@ -2494,26 +2411,21 @@ rs6000_debug_reg_global (void)
const char *name = processor_target_table[rs6000_tune_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_tune_index].target_enable;
- HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_tune_index);
sprintf (flags_buffer, "-mtune=%s flags", name);
- rs6000_print_isa_options (stderr, 0, flags_buffer, flags, arch_flags);
+ rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
cl_target_option_save (&cl_opts, &global_options, &global_options_set);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
- rs6000_isa_flags, 0);
+ rs6000_isa_flags);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
- rs6000_isa_flags_explicit, 0);
-
- if (rs6000_arch_flags)
- rs6000_print_isa_options (stderr, 0, "rs6000_arch_flags", 0,
- rs6000_arch_flags);
+ rs6000_isa_flags_explicit);
- rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
+ rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
@@ -3701,6 +3613,7 @@ rs6000_option_override_internal (bool global_init_p)
bool ret = true;
HOST_WIDE_INT set_masks;
+ HOST_WIDE_INT ignore_masks;
int cpu_index = -1;
int tune_index;
struct cl_target_option *main_target_opt
@@ -3709,7 +3622,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Print defaults. */
if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
- rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
+ rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
/* Remember the explicit arguments. */
if (global_init_p)
@@ -3840,8 +3753,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
}
- rs6000_arch_flags = get_arch_flags (cpu_index);
-
/* Don't expect powerpc64 enabled on those OSes with OS_MISSING_POWERPC64,
since they do not save and restore the high half of the GPRs correctly
in all cases. If the user explicitly specifies it, we won't interfere
@@ -3909,7 +3820,8 @@ rs6000_option_override_internal (bool global_init_p)
/* If little-endian, default to -mstrict-align on older processors. */
if (!BYTES_BIG_ENDIAN
- && (get_arch_flags (tune_index) & ARCH_MASK_POWER8) == 0)
+ && !(processor_target_table[tune_index].target_enable
+ & OPTION_MASK_POWER8))
rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
/* Add some warnings for VSX. */
@@ -3960,8 +3872,7 @@ rs6000_option_override_internal (bool global_init_p)
& ~rs6000_isa_flags_explicit);
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
#ifdef XCOFF_DEBUGGING_INFO
/* For AIX default to 64-bit DWARF. */
@@ -3969,13 +3880,59 @@ rs6000_option_override_internal (bool global_init_p)
dwarf_offset_size = POINTER_SIZE_UNITS;
#endif
- /* Report trying to use things like -mmodulo to imply -mcpu=power9. */
- report_architecture_mismatch ();
+ /* Handle explicit -mno-{altivec,vsx} and turn off all of
+ the options that depend on those flags. */
+ ignore_masks = rs6000_disable_incompatible_switches ();
+
+ /* For the newer switches (vsx, dfp, etc.) set some of the older options,
+ unless the user explicitly used the -mno-<option> to disable the code. */
+ if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+ rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_P9_MINMAX)
+ {
+ if (cpu_index >= 0)
+ {
+ if (cpu_index == PROCESSOR_POWER9)
+ {
+ /* legacy behavior: allow -mcpu=power9 with certain
+ capabilities explicitly disabled. */
+ rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+ }
+ else
+ error ("power9 target option is incompatible with %<%s=<xxx>%> "
+ "for <xxx> less than power9", "-mcpu");
+ }
+ else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
+ != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
+ & rs6000_isa_flags_explicit))
+ /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
+ were explicitly cleared. */
+ error ("%qs incompatible with explicitly disabled options",
+ "-mpower9-minmax");
+ else
+ rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
+ }
+ else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
+ rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_VSX)
+ rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_POPCNTD)
+ rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
+ else if (TARGET_DFP)
+ rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_CMPB)
+ rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
+ else if (TARGET_FPRND)
+ rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
+ else if (TARGET_POPCNTB)
+ rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
+ else if (TARGET_ALTIVEC)
+ rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
/* Disable VSX and Altivec silently if the user switched cpus to power7 in a
target attribute or pragma which automatically enables both options,
unless the altivec ABI was set. This is set by default for 64-bit, but
- not for 32-bit. Don't move this before report_architecture_mismatch
+ not for 32-bit. Don't move this before the above code using ignore_masks,
since it can reset the cleared VSX/ALTIVEC flag again. */
if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
{
@@ -4277,8 +4234,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Print the options after updating the defaults. */
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
/* E500mc does "better" if we inline more aggressively. Respect the
user's opinion, though. */
@@ -4385,8 +4341,7 @@ rs6000_option_override_internal (bool global_init_p)
TARGET_NO_FP_IN_TOC = 1;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
@@ -4433,8 +4388,7 @@ rs6000_option_override_internal (bool global_init_p)
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
{
if (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
else
rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4454,8 +4408,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
&& rs6000_tune != PROCESSOR_POWER5
@@ -4465,7 +4418,6 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_tune != PROCESSOR_POWER9
&& rs6000_tune != PROCESSOR_POWER10
&& rs6000_tune != PROCESSOR_POWER11
- && rs6000_tune != PROCESSOR_FUTURE
&& rs6000_tune != PROCESSOR_PPCA2
&& rs6000_tune != PROCESSOR_CELL
&& rs6000_tune != PROCESSOR_PPC476);
@@ -4481,7 +4433,6 @@ rs6000_option_override_internal (bool global_init_p)
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_PPCE500MC
|| rs6000_tune == PROCESSOR_PPCE500MC64
|| rs6000_tune == PROCESSOR_PPCE5500
@@ -4782,7 +4733,6 @@ rs6000_option_override_internal (bool global_init_p)
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
rs6000_cost = &power10_cost;
break;
@@ -5949,30 +5899,27 @@ rs6000_machine_from_flags (void)
return "ppc64";
#endif
- HOST_WIDE_INT arch_flags = rs6000_arch_flags;
HOST_WIDE_INT flags = rs6000_isa_flags;
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
| OPTION_MASK_ALTIVEC);
- if ((arch_flags & ARCH_MASK_FUTURE) != 0)
- return "future";
- if ((arch_flags & ARCH_MASK_POWER11) != 0)
+ if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
return "power11";
- if ((arch_flags & ARCH_MASK_POWER10) != 0)
+ if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
- if ((arch_flags & ARCH_MASK_POWER9) != 0)
+ if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
return "power9";
- if ((arch_flags & ARCH_MASK_POWER8) != 0)
+ if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
return "power8";
- if ((arch_flags & ARCH_MASK_POWER7) != 0)
+ if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
return "power7";
- if ((arch_flags & ARCH_MASK_POWER6) != 0)
+ if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
return "power6";
- if ((arch_flags & ARCH_MASK_POWER5) != 0)
+ if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
return "power5";
- if ((arch_flags & ARCH_MASK_POWER4) != 0)
+ if ((flags & ISA_2_1_MASKS) != 0)
return "power4";
if ((flags & OPTION_MASK_POWERPC64) != 0)
return "ppc64";
@@ -10209,7 +10156,6 @@ rs6000_reassociation_width (unsigned int opc
ATTRIBUTE_UNUSED,
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
if (DECIMAL_FLOAT_MODE_P (mode))
return 1;
if (VECTOR_MODE_P (mode))
@@ -18297,8 +18243,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
/* Separate a load from a narrower, dependent store. */
if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& MEM_P (XEXP (PATTERN (insn), 1))
@@ -18338,7 +18283,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_CELL)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0))
@@ -18914,7 +18858,6 @@ rs6000_issue_rate (void)
return 6;
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
return 8;
default:
return 1;
@@ -19630,11 +19573,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED,
int sched_verbose,
if (rs6000_tune == PROCESSOR_POWER6)
load_store_pendulum = 0;
- /* Do Power10/Power11/future dependent reordering. */
+ /* Do Power10/Power11 dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE))
+ || rs6000_tune == PROCESSOR_POWER11))
power10_sched_reorder (ready, n_ready - 1);
return rs6000_issue_rate ();
@@ -19658,11 +19600,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose,
rtx_insn **ready,
&& recog_memoized (last_scheduled_insn) >= 0)
return power9_sched_reorder2 (ready, *pn_ready - 1);
- /* Do Power10/Power11/future dependent reordering. */
+ /* Do Power10/Power11 dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE))
+ || rs6000_tune == PROCESSOR_POWER11))
return power10_sched_reorder (ready, *pn_ready - 1);
return cached_can_issue_more;
@@ -22490,7 +22431,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case POPCOUNT:
- *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
+ *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
return false;
case PARITY:
@@ -22880,8 +22821,7 @@ rs6000_register_move_cost (machine_mode mode,
out to be a nop. */
if (rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
else
ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -23278,7 +23218,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
rtx tmp1, tmp2;
/* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
- if (TARGET_POWER7)
+ if (TARGET_POPCNTD)
{
if (mode == SImode)
emit_insn (gen_popcntdsi2 (dst, src));
@@ -24551,6 +24491,8 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
+ { "power10", OPTION_MASK_POWER10, false, true },
+ { "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
@@ -24607,23 +24549,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[]
=
{ "string", 0, false, false },
};
-/* Similar structure for the arch bits that are set via -mcpu=<xxx> and not via
- a separate -m<yyy> option. */
-struct rs6000_arch_mask {
- const char *name; /* option name */
- const HOST_WIDE_INT mask; /* mask to set */
-};
-
-#undef ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME) { NAME, ARCH_MASK_ ## PROC },
-
-static struct rs6000_arch_mask const rs6000_arch_masks[] =
-{
-#include "rs6000-arch.def"
-};
-
-#undef ARCH_EXPAND
-
/* Option variables that we want to support inside attribute((target)) and
#pragma GCC target operations. */
@@ -24982,7 +24907,6 @@ rs6000_pragma_target_parse (tree args, tree pop_target)
tree cur_tree;
struct cl_target_option *prev_opt, *cur_opt;
HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
- HOST_WIDE_INT prev_arch, cur_arch, diff_arch;
if (TARGET_DEBUG_TARGET)
{
@@ -25035,26 +24959,21 @@ rs6000_pragma_target_parse (tree args, tree
pop_target)
{
prev_opt = TREE_TARGET_OPTION (prev_tree);
prev_flags = prev_opt->x_rs6000_isa_flags;
- prev_arch = prev_opt->x_rs6000_arch_flags;
cur_opt = TREE_TARGET_OPTION (cur_tree);
cur_flags = cur_opt->x_rs6000_isa_flags;
- cur_arch = cur_opt->x_rs6000_arch_flags;
diff_flags = (prev_flags ^ cur_flags);
- diff_arch = (prev_arch ^ cur_arch);
- if (diff_flags != 0 || diff_arch != 0)
+ if (diff_flags != 0)
{
/* Delete old macros. */
rs6000_target_modify_macros_ptr (false,
- prev_flags & diff_flags,
- prev_arch & diff_arch);
+ prev_flags & diff_flags);
/* Define new macros. */
rs6000_target_modify_macros_ptr (true,
- cur_flags & diff_flags,
- cur_arch & diff_arch);
+ cur_flags & diff_flags);
}
}
@@ -25168,7 +25087,6 @@ rs6000_function_specific_save (struct cl_target_option
*ptr,
{
ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
- ptr->x_rs6000_arch_flags = opts->x_rs6000_arch_flags;
}
/* Restore the current options */
@@ -25181,7 +25099,6 @@ rs6000_function_specific_restore (struct gcc_options
*opts,
{
opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
- opts->x_rs6000_arch_flags = ptr->x_rs6000_arch_flags;
(void) rs6000_option_override_internal (false);
}
@@ -25192,12 +25109,10 @@ rs6000_function_specific_print (FILE *file, int
indent,
struct cl_target_option *ptr)
{
rs6000_print_isa_options (file, indent, "Isa options set",
- ptr->x_rs6000_isa_flags,
- ptr->x_rs6000_arch_flags);
+ ptr->x_rs6000_isa_flags);
rs6000_print_isa_options (file, indent, "Isa options explicit",
- ptr->x_rs6000_isa_flags_explicit,
- ptr->x_rs6000_arch_flags);
+ ptr->x_rs6000_isa_flags_explicit);
}
/* Helper function to print the current isa or misc options on a line. */
@@ -25209,18 +25124,13 @@ rs6000_print_options_internal (FILE *file,
HOST_WIDE_INT flags,
const char *prefix,
const struct rs6000_opt_mask *opts,
- size_t num_elements,
- HOST_WIDE_INT arch_flags,
- const char *arch_prefix,
- const struct rs6000_arch_mask *arch_masks,
- size_t num_arch)
+ size_t num_elements)
{
size_t i;
size_t start_column = 0;
size_t cur_column;
size_t max_column = 120;
size_t prefix_len = strlen (prefix);
- size_t arch_prefix_len = strlen (arch_prefix);
size_t comma_len = 0;
const char *comma = "";
@@ -25280,29 +25190,6 @@ rs6000_print_options_internal (FILE *file,
comma_len = strlen (", ");
}
- /* Put out the architecture flag bits that are set via -mcpu=<xxx> and that
- don't have a -m option. */
- for (i = 0; i < num_arch; i++)
- {
- if ((arch_flags & arch_masks[i].mask) != 0)
- {
- const char *name = arch_masks[i].name;
- size_t len = comma_len + arch_prefix_len + strlen (name);
-
- cur_column += len;
- if (cur_column > max_column)
- {
- fprintf (stderr, ", \\\n%*s", (int)start_column, "");
- cur_column = start_column + len;
- comma = "";
- }
-
- fprintf (file, "%s%s%s", comma, arch_prefix, name);
- comma = ", ";
- comma_len = strlen (", ");
- }
- }
-
fputs ("\n", file);
}
@@ -25310,13 +25197,11 @@ rs6000_print_options_internal (FILE *file,
static void
rs6000_print_isa_options (FILE *file, int indent, const char *string,
- HOST_WIDE_INT flags, HOST_WIDE_INT arch_flags)
+ HOST_WIDE_INT flags)
{
rs6000_print_options_internal (file, indent, string, flags, "-m",
&rs6000_opt_masks[0],
- ARRAY_SIZE (rs6000_opt_masks),
- arch_flags, "arch=", &rs6000_arch_masks[0],
- ARRAY_SIZE (rs6000_arch_masks));
+ ARRAY_SIZE (rs6000_opt_masks));
}
/* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
@@ -25379,81 +25264,6 @@ rs6000_disable_incompatible_switches (void)
return ignore_masks;
}
-/* In the past, we would boost up the ISA if you selected an -m<foo> option but
- did not specify the correct -mcpu=<bar> option. I.e. if you added -mvsx,
- GCC implictly would assume that you were building for at least power7. Now,
- don't allow the -m<foo> option to boost up the ISA level. But you can still
- do -mcpu=power7 -mno-vsx or -mcpu=power5 -mno-vsx. */
-
-static void
-report_architecture_mismatch (void)
-{
- HOST_WIDE_INT ignore_masks = rs6000_disable_incompatible_switches ();
-
- static const struct {
- const HOST_WIDE_INT isa_flags; /* -m<foo> optiona. */
- const HOST_WIDE_INT arch_flags; /* -mcpu=<proc> level. */
- const char *const arch_name; /* architecture needed. */
- } mismatches[] = {
- {
- OPTION_MASK_P9_VECTOR | OPTION_MASK_P9_MISC | OPTION_MASK_P9_MINMAX
- | OPTION_MASK_MODULO,
- ARCH_MASK_POWER9,
- "-mcpu=power9"
- },
-
- {
- OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO,
- ARCH_MASK_POWER8,
- "-mcpu=power8"
- },
-
- {
- OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
- ARCH_MASK_POWER7,
- "-mcpu=power7"
- },
- };
-
- HOST_WIDE_INT isa_flags = rs6000_isa_flags;
- HOST_WIDE_INT arch_flags = rs6000_arch_flags;
-
- for (size_t i = 0; i < ARRAY_SIZE (mismatches); i++)
- {
- HOST_WIDE_INT mismatch_isa_flags = mismatches[i].isa_flags & isa_flags;
- HOST_WIDE_INT mismatch_arch_flags = mismatches[i].arch_flags &
arch_flags;
-
- if (mismatch_isa_flags != 0 && mismatch_arch_flags == 0)
- {
- for (size_t j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
- {
- HOST_WIDE_INT mask = rs6000_opt_masks[j].mask;
-
- if ((mask & mismatch_isa_flags) != 0
- && (mask & rs6000_isa_flags_explicit) != 0)
- error ("%qs needs at least %qs",
- rs6000_opt_masks[j].name,
- mismatches[i].arch_name);
- }
-
- rs6000_isa_flags &= ~mismatch_isa_flags;
- }
- }
-
- /* The following old options are used in multiple processors, so silently
- enable the appropriate ISA options as previous GCC revisions did. */
- if (TARGET_DFP)
- rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_CMPB)
- rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_POWER5X)
- rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
- else if (TARGET_POPCNTB)
- rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
- else if (TARGET_ALTIVEC)
- rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
-}
-
/* Helper function for printing the function name when debugging. */
@@ -25481,7 +25291,7 @@ static int
rs6000_clone_priority (tree fndecl)
{
tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
- HOST_WIDE_INT arch_masks;
+ HOST_WIDE_INT isa_masks;
int ret = CLONE_DEFAULT;
tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
const char *attrs_str = NULL;
@@ -25497,12 +25307,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
- arch_masks = rs6000_arch_flags;
+ isa_masks = rs6000_isa_flags;
else
- arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
+ isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
for (ret = CLONE_MAX - 1; ret != 0; ret--)
- if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
+ if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
break;
}
@@ -25982,8 +25792,6 @@ rs6000_can_inline_p (tree caller, tree callee)
HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags;
HOST_WIDE_INT caller_isa = caller_opts->x_rs6000_isa_flags;
HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit;
- HOST_WIDE_INT callee_arch = callee_opts->x_rs6000_arch_flags;
- HOST_WIDE_INT caller_arch = caller_opts->x_rs6000_arch_flags;
cgraph_node *callee_node = cgraph_node::get (callee);
if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL)
@@ -26007,8 +25815,7 @@ rs6000_can_inline_p (tree caller, tree callee)
callee has explicitly enabled or disabled, then we must enforce that
the callee's and caller's options match exactly; see PR70010. */
if (((caller_isa & callee_isa) == callee_isa)
- && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)
- && (caller_arch & callee_arch) == callee_arch)
+ && (caller_isa & explicit_isa) == (callee_isa & explicit_isa))
ret = true;
if (TARGET_DEBUG_TARGET)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8cfd9faf77dc..d460eb065448 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -101,7 +101,6 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
@@ -443,28 +442,30 @@ extern int rs6000_vector_align[];
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
#define TARGET_IEEEQUAD rs6000_ieeequad
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POWER5) /* ISA 2.02 and above */ \
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_POWER6
-#define TARGET_LFIWZX TARGET_POWER7
-#define TARGET_FCFIDS TARGET_POWER7
-#define TARGET_FCFIDU TARGET_POWER7
-#define TARGET_FCFIDUS TARGET_POWER7
-#define TARGET_FCTIDUZ TARGET_POWER7
-#define TARGET_FCTIWUZ TARGET_POWER7
+#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWZX TARGET_POPCNTD
+#define TARGET_FCFIDS TARGET_POPCNTD
+#define TARGET_FCFIDU TARGET_POPCNTD
+#define TARGET_FCFIDUS TARGET_POPCNTD
+#define TARGET_FCTIDUZ TARGET_POPCNTD
+#define TARGET_FCTIWUZ TARGET_POPCNTD
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_POWER9
-#define TARGET_EXTSWSLI (TARGET_POWER9 && TARGET_POWERPC64)
-#define TARGET_MADDLD TARGET_POWER9
+#define TARGET_CTZ TARGET_MODULO
+#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
+#define TARGET_MADDLD TARGET_MODULO
/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -519,27 +520,6 @@ extern int rs6000_vector_align[];
#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
#endif
-/* In the past we represented the various power cpus (power4, power5, power6,
- etc.) via ISA bits that highlighted a new instruction or we used an extra
- option to represent the hardware (i.e. -mpower8-internal or -mpower10). Now
- we use architecture flags for this. */
-#define TARGET_POWER4 ((rs6000_arch_flags & ARCH_MASK_POWER4) != 0)
-#define TARGET_POWER5 ((rs6000_arch_flags & ARCH_MASK_POWER5) != 0)
-#define TARGET_POWER5X ((rs6000_arch_flags & ARCH_MASK_POWER5X) != 0)
-#define TARGET_POWER6 ((rs6000_arch_flags & ARCH_MASK_POWER6) != 0)
-#define TARGET_POWER7 ((rs6000_arch_flags & ARCH_MASK_POWER7) != 0)
-#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
-#define TARGET_POWER9 ((rs6000_arch_flags & ARCH_MASK_POWER9) != 0)
-#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
-#define TARGET_POWER11 ((rs6000_arch_flags & ARCH_MASK_POWER11) != 0)
-#define TARGET_FUTURE ((rs6000_arch_flags & ARCH_MASK_FUTURE) != 0)
-
-/* In the past we represented power8, power10 as an ISA bit and used internal
- switches the user was not supposed to use for -mpower8-internal and
- -mpower10. Now we use architecture flags for this. */
-#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
-#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
-
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
@@ -547,7 +527,9 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POWER5 /* ISA 2.02 & above */ \
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
@@ -561,9 +543,9 @@ extern int rs6000_vector_align[];
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
#define TARGET_FRE (TARGET_HARD_FLOAT \
- && (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
-#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POWER5 \
+#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
&& TARGET_PPC_GFXOPT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
@@ -1756,7 +1738,7 @@ typedef struct rs6000_args
zero. The hardware instructions added in Power9 and the sequences using
popcount return 32 or 64. */
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
- (TARGET_CTZ || TARGET_POWER7 \
+ (TARGET_CTZ || TARGET_POPCNTD
\
? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
: ((VALUE) = -1, 2))
@@ -2501,27 +2483,3 @@ while (0)
issues have been resolved. */
#define RS6000_DISABLE_SCALAR_MODULO 1
-
-
-/* Create the architecture flags. */
-/* Define an enumeration to number the architecture masks. */
-#ifdef GCC_HWINT_H
-#undef ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME) ARCH_ENUM_ ## PROC,
-
-enum {
-#include "rs6000-arch.def"
- ARCH_ENUM_LAST
-};
-
-/* Create an architecture mask for the newer architectures (power6 and
- up).. */
-#undef ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)
\
- static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
- = HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
-
-#include "rs6000-arch.def"
-
-#undef ARCH_EXPAND
-#endif /* GCC_HWINT_H. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6642a4717963..8eda2f7bb0d7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -364,7 +364,7 @@
ppc750,ppc7400,ppc7450,
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
- power4,power5,power6,power7,power8,power9,power10,power11,future,
+ power4,power5,power6,power7,power8,power9,power10,power11,
rs64a,mpccore,cell,ppca2,titan"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
@@ -379,15 +379,15 @@
(const_int 1)
(and (eq_attr "isa" "p5")
- (match_test "TARGET_POWER5"))
+ (match_test "TARGET_POPCNTB"))
(const_int 1)
(and (eq_attr "isa" "p6")
- (match_test "TARGET_POWER6"))
+ (match_test "TARGET_CMPB"))
(const_int 1)
(and (eq_attr "isa" "p7")
- (match_test "TARGET_POWER7"))
+ (match_test "TARGET_POPCNTD"))
(const_int 1)
(and (eq_attr "isa" "p7v")
@@ -403,7 +403,7 @@
(const_int 1)
(and (eq_attr "isa" "p9")
- (match_test "TARGET_POWER9"))
+ (match_test "TARGET_MODULO"))
(const_int 1)
(and (eq_attr "isa" "p9v")
@@ -2466,7 +2466,7 @@
rtx tmp2 = gen_reg_rtx (<MODE>mode);
rtx tmp3 = gen_reg_rtx (<MODE>mode);
- if (TARGET_POWER7)
+ if (TARGET_POPCNTD)
{
emit_insn (gen_add<mode>3 (tmp1, operands[1], constm1_rtx));
emit_insn (gen_one_cmpl<mode>2 (tmp2, operands[1]));
@@ -2510,7 +2510,7 @@
(define_expand "popcount<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB || TARGET_POPCNTD"
{
rs6000_emit_popcount (operands[0], operands[1]);
DONE;
@@ -2520,14 +2520,14 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_POPCNTB))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB"
"popcntb %0,%1"
[(set_attr "type" "popcnt")])
(define_insn "popcntd<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"popcnt<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2535,7 +2535,7 @@
(define_expand "parity<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB"
{
rs6000_emit_parity (operands[0], operands[1]);
DONE;
@@ -2544,7 +2544,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_POWER6"
+ "TARGET_CMPB && TARGET_POPCNTB"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2597,7 +2597,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
- "TARGET_POWER6"
+ "TARGET_CMPB"
"cmpb %0,%1,%2"
[(set_attr "type" "cmp")])
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_POWER5X
+ && TARGET_FPRND
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_POWER5X
+ && TARGET_FPRND
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
- || TARGET_POWER6
+ || TARGET_CMPB
|| VECTOR_UNIT_VSX_P (<MODE>mode))"
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
if (!gpc_reg_operand (operands[2], <MODE>mode))
operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
- if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
+ if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
{
emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
operands[2]));
@@ -5438,7 +5438,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
- "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
@@ -6687,7 +6687,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X
+ "TARGET_HARD_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -6784,7 +6784,7 @@
/* For those old archs in which SImode can't be hold in float registers,
call lrint<mode>si_di to put the result in DImode then convert it via
stack. */
- if (!TARGET_POWER7)
+ if (!TARGET_POPCNTD)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_lrint<mode>si_di (tmp, operands[1]));
@@ -6799,7 +6799,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && TARGET_POWER7"
+ "TARGET_HARD_FLOAT && TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6807,7 +6807,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && !TARGET_POWER7"
+ "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6815,7 +6815,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIZ))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIP))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIM))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FRIN))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"frin %0,%1"
[(set_attr "type" "fp")])
@@ -10122,7 +10122,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10144,7 +10144,7 @@
(compare:SI (match_operand:BLK 1)
(match_operand:BLK 2)))
(use (match_operand:SI 3))])]
- "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10168,7 +10168,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -14435,7 +14435,7 @@
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"bpermd %0,%1,%2"
[(set_attr "type" "popcnt")])
@@ -14813,7 +14813,7 @@
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
UNSPEC_ADDG6S))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"addg6s %0,%1,%2"
[(set_attr "type" "integer")])
@@ -14821,7 +14821,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CDTBCD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cdtbcd %0,%1"
[(set_attr "type" "integer")])
@@ -14829,7 +14829,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CBCDTD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cbcdtd %0,%1"
[(set_attr "type" "integer")])
@@ -14844,7 +14844,7 @@
(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
(match_operand:GPR 2 "register_operand" "r")]
UNSPEC_DIV_EXTEND))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"div<wd><div_extend> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 0d71dbaf2fc1..94323bd1db26 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -36,14 +36,6 @@ HOST_WIDE_INT rs6000_isa_flags_explicit
TargetSave
HOST_WIDE_INT x_rs6000_isa_flags_explicit
-;; Arch bits that are set via -mcpu=<xxx> but don't have a user -m<processor>
-;; option
-Variable
-HOST_WIDE_INT rs6000_arch_flags = 0
-
-TargetSave
-HOST_WIDE_INT x_rs6000_arch_flags
-
;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC603
@@ -478,8 +470,9 @@ Save the TOC in the prologue for indirect calls rather than
inline.
mvsx-timode
Target RejectNegative Undocumented Ignore
+;; This option exists only to create its MASK. It is not intended for users.
mpower8-internal
-Target Undocumented WarnRemoved
+Target Undocumented Mask(POWER8) Var(rs6000_isa_flags) Warn(Do not use
%<-mpower8-internal%>; use %<-mcpu=power8%> instead)
mpower8-fusion
Target Mask(P8_FUSION) Var(rs6000_isa_flags)
@@ -590,7 +583,13 @@ mspeculate-indirect-jumps
Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
mpower10
-Target Undocumented WarnRemoved
+Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
+
+;; Users should not use -mpower11, but we need to use a bit to identify when
+;; the user changes the default cpu via #pragma GCC target("cpu=power11")
+;; and then resets it later.
+mpower11
+Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) WarnRemoved
mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index 5e2ecf34f249..feef76db4618 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_fprs } */
/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
+/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
/* { dg-final { scan-assembler-times "fadds" 1 } } */
@@ -18,6 +18,10 @@
#error "__VSX__ should not be defined."
#endif
+#pragma GCC target("altivec,vsx")
+#include <altivec.h>
+#pragma GCC reset_options
+
#pragma GCC push_options
#pragma GCC target("altivec,no-vsx")
@@ -29,7 +33,6 @@
#error "__VSX__ should not be defined."
#endif
-/* Altivec build, generate vaddfp. */
void
av_add (vector float *a, vector float *b, vector float *c)
{
@@ -37,11 +40,10 @@ av_add (vector float *a, vector float *b, vector float *c)
unsigned long n = SIZE / 4;
for (i = 0; i < n; i++)
- a[i] = b[i] + c[i];
+ a[i] = vec_add (b[i], c[i]);
}
-/* cpu=power7 must be used to enable VSX. */
-#pragma GCC target("cpu=power7,vsx")
+#pragma GCC target("vsx")
#ifndef __ALTIVEC__
#error "__ALTIVEC__ should be defined."
@@ -51,7 +53,6 @@ av_add (vector float *a, vector float *b, vector float *c)
#error "__VSX__ should be defined."
#endif
-/* VSX build on power7, generate xsaddsp. */
void
vsx_add (vector float *a, vector float *b, vector float *c)
{
@@ -59,31 +60,11 @@ vsx_add (vector float *a, vector float *b, vector float *c)
unsigned long n = SIZE / 4;
for (i = 0; i < n; i++)
- a[i] = b[i] + c[i];
-}
-
-#pragma GCC target("cpu=power7,no-vsx")
-
-#ifndef __ALTIVEC__
-#error "__ALTIVEC__ should be defined."
-#endif
-
-#ifdef __VSX__
-#error "__VSX__ should not be defined."
-#endif
-
-/* Altivec build on power7 with no VSX, generate vaddfp. */
-void
-av2_add (vector float *a, vector float *b, vector float *c)
-{
- unsigned long i;
- unsigned long n = SIZE / 4;
-
- for (i = 0; i < n; i++)
- a[i] = b[i] + c[i];
+ a[i] = vec_add (b[i], c[i]);
}
#pragma GCC pop_options
+#pragma GCC target("no-vsx,no-altivec")
#ifdef __ALTIVEC__
#error "__ALTIVEC__ should not be defined."
@@ -93,7 +74,6 @@ av2_add (vector float *a, vector float *b, vector float *c)
#error "__VSX__ should not be defined."
#endif
-/* Default power5 build, generate scalar fadds. */
void
norm_add (float *a, float *b, float *c)
{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 00c7c301436a..5222e66ef170 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,8 +7,7 @@
/* Verify there is no ICE under 32 bit env. */
-/* cpu=power7 must be used to enable VSX. */
-__attribute__((target("cpu=power7,vsx")))
+__attribute__((target("vsx")))
int test (void)
{
return 0;
