https://gcc.gnu.org/g:91f163d8135da00d6edac03ea81d5c29a78582aa
commit 91f163d8135da00d6edac03ea81d5c29a78582aa
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Nov 14 18:06:55 2024 -0500
Change TARGET_FPRND to TARGET_POWER5X.
This patch changes TARGET_POWER5X to TARGET_POWER5 and OPTION_MASK_POWER5X
to
OPTION_MASK_POWER5. The -mfprnd switch is not being changed, just the name
of
the macros used to determine if the PowerPC processor supports ISA 2.4
(Power5x).
2024-11-14 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros):
Change
TARGET_FPRND to TARGET_POWER5X. Change OPTION_MASK_FPRND to
OPTION_MASK_POWER5X.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_4_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(464fp cpu definition): Likewise
(476fp cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.md (fmod<mode>3): Likewise.
(remainder<mode>3): Likewise.
(fctiwuz_<mode): Likewise.
(btrunc<mode>): Likewise.
("ceil<mode>2): Likewise.
(floor<mode>2): Likewise.
(round<mode>2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mfprnd): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 2 +-
gcc/config/rs6000/rs6000-cpus.def | 14 +++++++-------
gcc/config/rs6000/rs6000.cc | 10 +++++-----
gcc/config/rs6000/rs6000.md | 14 +++++++-------
gcc/config/rs6000/rs6000.opt | 6 ++++--
5 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index da3a9c2d8406..c9ef36b77639 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -424,7 +424,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
if ((flags & OPTION_MASK_POWER5) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
- if ((flags & OPTION_MASK_FPRND) != 0)
+ if ((flags & OPTION_MASK_POWER5X) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
if ((flags & OPTION_MASK_CMPB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d600f123d6a7..b347053576db 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -22,7 +22,7 @@
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS OPTION_MASK_MFCRF
#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
+#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
@@ -124,7 +124,7 @@
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
- | OPTION_MASK_FPRND \
+ | OPTION_MASK_POWER5X \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -185,10 +185,10 @@ RS6000_CPU ("464", PROCESSOR_PPC440,
OPTION_MASK_SOFT_FLOAT
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+ | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
- | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
+ | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -239,14 +239,14 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 |
OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_FPRND)
+ | OPTION_MASK_POWER5X)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
+ | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
+ | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8adac6fbc572..4a2d0250956e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
else if (TARGET_CMPB)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_FPRND)
+ else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
else if (TARGET_POWER5)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3949,12 +3949,12 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
}
- if (!TARGET_FPRND && TARGET_VSX)
+ if (!TARGET_POWER5X && TARGET_VSX)
{
- if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
+ if (rs6000_isa_flags_explicit & OPTION_MASK_POWER5X)
/* TARGET_VSX = 1 implies Power 7 and newer */
error ("%qs requires %qs", "-mvsx", "-mfprnd");
- rs6000_isa_flags &= ~OPTION_MASK_FPRND;
+ rs6000_isa_flags &= ~OPTION_MASK_POWER5X;
}
/* Assert !TARGET_VSX if !TARGET_ALTIVEC and make some adjustments
@@ -24490,7 +24490,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
false, true },
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
- { "fprnd", OPTION_MASK_FPRND, false, true },
+ { "fprnd", OPTION_MASK_POWER5X, false, true },
{ "power10", OPTION_MASK_POWER10, false, true },
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d4cdfbb3095a..1ad2d46a1fbf 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_FPRND
+ && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_FPRND
+ && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -6687,7 +6687,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
- "TARGET_HARD_FLOAT && TARGET_FPRND
+ "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -6815,7 +6815,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIZ))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIP))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIM))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FRIN))]
- "TARGET_HARD_FLOAT && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_POWER5X"
"frin %0,%1"
[(set_attr "type" "fp")])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 24f2af208856..797fd9a77d76 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -134,9 +134,11 @@ mpopcntb
Target Mask(POWER5) Var(rs6000_isa_flags)
Use ISA 2.2 (Power5) instructions.
+;; Originally, we used -mfprnd to indicate ISA 2.4. Keep the switch name,
+;; but change the target macro.
mfprnd
-Target Mask(FPRND) Var(rs6000_isa_flags)
-Use PowerPC V2.02 floating point rounding instructions.
+Target Mask(POWER5X) Var(rs6000_isa_flags)
+Use ISA 2.4 (Power5x) instructions.
mcmpb
Target Mask(CMPB) Var(rs6000_isa_flags)
