https://gcc.gnu.org/g:12e30d82cc7ef614ec7a7f2bfae219fe8f99d94b
commit r15-5857-g12e30d82cc7ef614ec7a7f2bfae219fe8f99d94b
Author: Pan Li <pan2...@intel.com>
Date: Fri Nov 29 11:57:34 2024 +0800
RISC-V: Fix incorrect optimization options passing to widden
Like the strided load/store, the testcases of vector widen are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.
This patch would like to make it correct almost the same as what we fixed
for
strided load/store.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
options passing to testcases.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 8f5860c46b42..87c5ecb1a8b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -90,7 +90,7 @@ set AUTOVEC_TEST_OPTS [list \
{-ftree-vectorize -O2 -mrvv-max-lmul=m4} ]
foreach op $AUTOVEC_TEST_OPTS {
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/widen/*.\[cS\]]]
\
- "" "$op"
+ "$op" ""
}
# VLS-VLMAX tests
