[gcc r15-6460] [RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:7cea821aaceeec9a6a960392f49346d52d1bd54a

commit r15-6460-g7cea821aaceeec9a6a960392f49346d52d1bd54a
Author: Jeff Law <j...@ventanamicro.com>
Date:   Sun Dec 29 16:34:52 2024 -0700

    [RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern
    
    So for this bug we have what appears to me to just be a bogus pattern.
    
    Essentially the pattern tries to detect cases where we have an SI mode value
    and we can use the Zbs instructions to manipulate a bit. Conceptually that's
    great.
    
    The problem is the pattern assumes that SI objects are sign extended. It 
uses a
    test to try and filter out a problematical case (subregs), but that simply
    won't work with late-combine since the subreg will be stripped away and we 
have
    no way of knowing if the SI value was already sign extended to 64 bits or 
not.
    
    You might think we could look for a way to salvage the pattern and make it 
only
    usable prior to register allocation.  I pondered that extensively, but
    ultimately concluded that with the introduction of ext-dce it wasn't safe.
    
    So this just removes the problematical pattern.  Thankfully there aren't any
    regressions in the testsuite.  Even the test designed to test this pattern's
    applicability still generates the desired code.
    
    Changes since v1:
      - Adjust testcase so that it works for rv32 and rv64.
      - Adjust PR number in subject line.
    
            PR target/116715
    gcc/
            * config/riscv/bitmanip.md: Drop bogus pattern.
    
    gcc/testsuite
            * gcc.target/riscv/pr116715.c: New test.

Diff:
---
 gcc/config/riscv/bitmanip.md              | 12 ------------
 gcc/testsuite/gcc.target/riscv/pr116715.c | 18 ++++++++++++++++++
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 23dc47eaaefc..8f9b456dd823 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -790,18 +790,6 @@
   "<bit_optab>i\t%0,%1,%S2"
   [(set_attr "type" "bitmanip")])
 
-;; As long as the SImode operand is not a partial subreg, we can use a
-;; bseti without postprocessing, as the middle end is smart enough to
-;; stay away from the signbit.
-(define_insn "*<bit_optab>idisi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (any_or:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-                  (match_operand 2 "single_bit_mask_operand" "i")))]
-  "TARGET_ZBS && TARGET_64BIT
-   && !partial_subreg_p (operands[1])"
-  "<bit_optab>i\t%0,%1,%S2"
-  [(set_attr "type" "bitmanip")])
-
 ;; We can easily handle zero extensions
 (define_split
   [(set (match_operand:DI 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/pr116715.c 
b/gcc/testsuite/gcc.target/riscv/pr116715.c
new file mode 100644
index 000000000000..55daab20171e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr116715.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64d" { target { riscv64*-*-* } } } 
*/
+/* { dg-options "-march=rv32gc_zbs -mabi=ilp32" { target { riscv32*-*-* } } } 
*/
+#include <stdint-gcc.h>
+int32_t a, b;
+int32_t d;
+int64_t f = 695372830942;
+int main() {
+  d = 0;
+  for (; d < 1; d = 1)
+    --f;
+  d |= b = f;
+  int64_t h = d;
+  a = h >> 40;
+  if (a != -1)
+    __builtin_abort ();
+  __builtin_exit (0);
+}