https://gcc.gnu.org/g:18d3b87b17fd6157e3aff64099a5bf84ea5f82f3
commit r15-6489-g18d3b87b17fd6157e3aff64099a5bf84ea5f82f3
Author: Guo Jie <guo...@loongson.cn>
Date: Mon Dec 30 10:37:57 2024 +0800
LoongArch: Fix bugs in insn patterns lasx_xvrepl128vei_b/h/w/d_internal
There are two aspects that affect the matching of instruction templates:
1. vec_duplicate is redundant in the following operations.
set (match_operand:V4DI ...)
(vec_duplicate:V4DI (vec_select:V4DI ...))
2. The range of values for testing predicate const_8_to_15_operand and
const_16_to_31_operand should be [8, 15] and [16, 31] respectively.
However, there is currently no suitable testcase to verify.
gcc/ChangeLog:
* config/loongarch/lasx.md: Remove useless vec_select.
* config/loongarch/predicates.md: Correct error predicate.
Diff:
---
gcc/config/loongarch/lasx.md | 76 ++++++++++++++++++--------------------
gcc/config/loongarch/predicates.md | 4 +-
2 files changed, 38 insertions(+), 42 deletions(-)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index df91016037f9..1a320a05222f 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -2281,21 +2281,20 @@
(define_insn "lasx_xvrepl128vei_b_internal"
[(set (match_operand:V32QI 0 "register_operand" "=f")
- (vec_duplicate:V32QI
- (vec_select:V32QI
- (match_operand:V32QI 1 "register_operand" "f")
- (parallel [(match_operand 2 "const_uimm4_operand" "")
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_operand 3 "const_16_to_31_operand" "")
- (match_dup 3) (match_dup 3) (match_dup 3)
- (match_dup 3) (match_dup 3) (match_dup 3)
- (match_dup 3) (match_dup 3) (match_dup 3)
- (match_dup 3) (match_dup 3) (match_dup 3)
- (match_dup 3) (match_dup 3) (match_dup 3)]))))]
+ (vec_select:V32QI
+ (match_operand:V32QI 1 "register_operand" "f")
+ (parallel [(match_operand 2 "const_uimm4_operand" "")
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_operand 3 "const_16_to_31_operand" "")
+ (match_dup 3) (match_dup 3) (match_dup 3)
+ (match_dup 3) (match_dup 3) (match_dup 3)
+ (match_dup 3) (match_dup 3) (match_dup 3)
+ (match_dup 3) (match_dup 3) (match_dup 3)
+ (match_dup 3) (match_dup 3) (match_dup 3)])))]
"ISA_HAS_LASX && ((INTVAL (operands[3]) - INTVAL (operands[2])) == 16)"
"xvrepl128vei.b\t%u0,%u1,%2"
[(set_attr "type" "simd_splat")
@@ -2303,17 +2302,16 @@
(define_insn "lasx_xvrepl128vei_h_internal"
[(set (match_operand:V16HI 0 "register_operand" "=f")
- (vec_duplicate:V16HI
- (vec_select:V16HI
- (match_operand:V16HI 1 "register_operand" "f")
- (parallel [(match_operand 2 "const_uimm3_operand" "")
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_dup 2)
- (match_operand 3 "const_8_to_15_operand" "")
- (match_dup 3) (match_dup 3) (match_dup 3)
- (match_dup 3) (match_dup 3) (match_dup 3)
- (match_dup 3)]))))]
+ (vec_select:V16HI
+ (match_operand:V16HI 1 "register_operand" "f")
+ (parallel [(match_operand 2 "const_uimm3_operand" "")
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_dup 2)
+ (match_operand 3 "const_8_to_15_operand" "")
+ (match_dup 3) (match_dup 3) (match_dup 3)
+ (match_dup 3) (match_dup 3) (match_dup 3)
+ (match_dup 3)])))]
"ISA_HAS_LASX && ((INTVAL (operands[3]) - INTVAL (operands[2])) == 8)"
"xvrepl128vei.h\t%u0,%u1,%2"
[(set_attr "type" "simd_splat")
@@ -2321,13 +2319,12 @@
(define_insn "lasx_xvrepl128vei_w_internal"
[(set (match_operand:V8SI 0 "register_operand" "=f")
- (vec_duplicate:V8SI
- (vec_select:V8SI
- (match_operand:V8SI 1 "register_operand" "f")
- (parallel [(match_operand 2 "const_0_to_3_operand" "")
- (match_dup 2) (match_dup 2) (match_dup 2)
- (match_operand 3 "const_4_to_7_operand" "")
- (match_dup 3) (match_dup 3) (match_dup 3)]))))]
+ (vec_select:V8SI
+ (match_operand:V8SI 1 "register_operand" "f")
+ (parallel [(match_operand 2 "const_0_to_3_operand" "")
+ (match_dup 2) (match_dup 2) (match_dup 2)
+ (match_operand 3 "const_4_to_7_operand" "")
+ (match_dup 3) (match_dup 3) (match_dup 3)])))]
"ISA_HAS_LASX && ((INTVAL (operands[3]) - INTVAL (operands[2])) == 4)"
"xvrepl128vei.w\t%u0,%u1,%2"
[(set_attr "type" "simd_splat")
@@ -2335,13 +2332,12 @@
(define_insn "lasx_xvrepl128vei_d_internal"
[(set (match_operand:V4DI 0 "register_operand" "=f")
- (vec_duplicate:V4DI
- (vec_select:V4DI
- (match_operand:V4DI 1 "register_operand" "f")
- (parallel [(match_operand 2 "const_0_or_1_operand" "")
- (match_dup 2)
- (match_operand 3 "const_2_or_3_operand" "")
- (match_dup 3)]))))]
+ (vec_select:V4DI
+ (match_operand:V4DI 1 "register_operand" "f")
+ (parallel [(match_operand 2 "const_0_or_1_operand" "")
+ (match_dup 2)
+ (match_operand 3 "const_2_or_3_operand" "")
+ (match_dup 3)])))]
"ISA_HAS_LASX && ((INTVAL (operands[3]) - INTVAL (operands[2])) == 2)"
"xvrepl128vei.d\t%u0,%u1,%2"
[(set_attr "type" "simd_splat")
diff --git a/gcc/config/loongarch/predicates.md
b/gcc/config/loongarch/predicates.md
index e744e4e61ea8..25b7f9ffd186 100644
--- a/gcc/config/loongarch/predicates.md
+++ b/gcc/config/loongarch/predicates.md
@@ -267,11 +267,11 @@
(define_predicate "const_8_to_15_operand"
(and (match_code "const_int")
- (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
+ (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
(define_predicate "const_16_to_31_operand"
(and (match_code "const_int")
- (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
+ (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
(define_predicate "qi_mask_operand"
(and (match_code "const_int")
