https://gcc.gnu.org/g:b9493e98da58c7689645b4ee1a2f653b86a5d758
commit r15-7021-gb9493e98da58c7689645b4ee1a2f653b86a5d758
Author: Jin Ma <ji...@linux.alibaba.com>
Date: Sat Jan 18 07:43:17 2025 -0700
[PR target/118357] RISC-V: Disable fusing vsetvl instructions by
VSETVL_VTYPE_CHANGE_ONLY for XTheadVector.
In RVV 1.0, the instruction "vsetvli zero,zero,*" indicates that the
available vector length (avl) does not change. However, in XTheadVector,
this same instruction signifies that the avl should take the maximum value.
Consequently, when fusing vsetvl instructions, the optimization labeled
"VSETVL_VTYPE_CHANGE_ONLY" is disabled for XTheadVector.
PR target/118357
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: Function change_vtype_only_p always
returns false for XTheadVector.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr118357.c: New test.
Diff:
---
gcc/config/riscv/riscv-vsetvl.cc | 3 ++-
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c | 13 +++++++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index a4016beebc0c..72c4c59514e5 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -903,7 +903,8 @@ public:
bool valid_p () const { return m_state == state_type::VALID; }
bool unknown_p () const { return m_state == state_type::UNKNOWN; }
bool empty_p () const { return m_state == state_type::EMPTY; }
- bool change_vtype_only_p () const { return m_change_vtype_only; }
+ bool change_vtype_only_p () const { return m_change_vtype_only
+ && !TARGET_XTHEADVECTOR; }
void set_valid () { m_state = state_type::VALID; }
void set_unknown () { m_state = state_type::UNKNOWN; }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c
new file mode 100644
index 000000000000..aebb0e3088ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2" } */
+
+#include <riscv_vector.h>
+
+vfloat16m4_t foo (float *ptr, size_t vl)
+{
+ vfloat32m8_t _p = __riscv_vle32_v_f32m8 (ptr, vl);
+ vfloat16m4_t _half = __riscv_vfncvt_f_f_w_f16m4 (_p, vl);
+ return _half;
+}
+
+/* { dg-final { scan-assembler-not {th.vsetvli\tzero,zero} } }*/
