https://gcc.gnu.org/g:b22f191b7c594b33fb4b4a07769dbf0ca45bc9e9
commit r15-7601-gb22f191b7c594b33fb4b4a07769dbf0ca45bc9e9
Author: Jin Ma <ji...@linux.alibaba.com>
Date: Mon Feb 17 10:43:22 2025 +0800
RISC-V: Fix failed tests for regression due to fix ICE patch
Ref:
https://github.com/ewlu/gcc-precommit-ci/issues/3096#issue-2854419069
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-9.c: Added new failure check.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c:
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c:
Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c | 1 +
.../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c | 1 +
15 files changed, 15 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
index 20ae9ebf6f22..8cfe96588751 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
@@ -11,3 +11,4 @@ vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t
vl)
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
index a064417169d8..ebe31f5c961b 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
}
/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or
v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
index 61d3fb25dc2d..7e9a101795dc 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f,
zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
\ No newline at end of file
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
index bfc26f8210ac..b5354f4291f9 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
index 35a2924234f2..c1a574d5e294 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
index e3aef339d68d..62c2815fdad1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
}
/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or
v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
index b5a894ecad43..f0b72e5060b2 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
index 7267fa3304b7..9f22a182d4ca 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
index 5a7c4481a5a9..1006ad4af186 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f,
zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
index f1241cb17714..de36e4310b02 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
index 2738a29d6736..f87f8c54c8de 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
index 8610000b4740..c5bc8511b677 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
@@ -11,3 +11,4 @@ test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat64m1_t' requires the zve64d or v ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
index 7eaa6adab826..738d2e627486 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
index eb74e33299fa..f82ad41cd50e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
@@ -11,3 +11,4 @@ test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
}
/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
index 590343ddbfde..b9aceb83682f 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
@@ -11,3 +11,4 @@ test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
}
/* { dg-error "return type 'vint32m1_t' requires the V ISA extension" "" {
target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint32m1_t' requires the V ISA extension" "" {
target { "riscv*-*-*" } } 0 } */
