https://gcc.gnu.org/g:7b7c0fe37332290fad9b31bf3ae05c28375e0a76
commit r15-8926-g7b7c0fe37332290fad9b31bf3ae05c28375e0a76
Author: Jakub Jelinek <ja...@redhat.com>
Date: Wed Mar 26 12:19:14 2025 +0100
i386: Fix up pr55583.c testcase [PR119465]
In r15-4289 H.J. fixed up the pr55583.c testcase to use unsigned long long
or long long instead of unsigned long or long. That change looks correct to
me because the
void test64r () { b = ((u64)b >> n) | (a << (64 - n)); }
etc. functions otherwise aren't really 64-bit rotates, but something that
triggers UB all the time (at least one of the shifts is out of bounds).
I assume that change fixed the FAILs on -mx32, but it caused
FAIL: gcc.target/i386/pr55583.c scan-assembler-times (?n)shldl?[\\\\t
]*\\\\\$2 1
FAIL: gcc.target/i386/pr55583.c scan-assembler-times (?n)shrdl?[\\\\t
]*\\\\\$2 2
regression on i686-linux (but just for -m32 without defaulting to SSE2 or
what). The difference is that for say -m32 -march=x86-64 the stv pass
handles some of the rotates in SSE and so we get different sh[rl]dl
instruction counts from the case when SSE isn't enabled and stv pass isn't
done.
The following patch fixes that by disabling SSE for ia32 and always testing
for the same number of instructions.
Tested with all of
make check-gcc
RUNTESTFLAGS='--target_board=unix\{-m32/-march=x86-64,-m32/-march=i686,-mx32,-m64\}
i386.exp=pr55583.c'
2025-03-26 Jakub Jelinek <ja...@redhat.com>
PR target/55583
PR target/119465
* gcc.target/i386/pr55583.c: Add -mno-sse -mno-mmx to
dg-additional-options. Expect 4 shrdl and 2 shldl instructions on
ia32.
Diff:
---
gcc/testsuite/gcc.target/i386/pr55583.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/i386/pr55583.c
b/gcc/testsuite/gcc.target/i386/pr55583.c
index ea6a2d54c495..87734518417d 100644
--- a/gcc/testsuite/gcc.target/i386/pr55583.c
+++ b/gcc/testsuite/gcc.target/i386/pr55583.c
@@ -1,9 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O2 -Wno-shift-count-overflow" } */
-/* { dg-final { scan-assembler-times {(?n)shrd[ql]?[\t ]*\$2} 4 { target { !
ia32 } } } } */
-/* { dg-final { scan-assembler-times {(?n)shrdl?[\t ]*\$2} 2 { target ia32 } }
} */
-/* { dg-final { scan-assembler-times {(?n)shldl?[\t ]*\$2} 1 { target ia32 } }
} */
-/* { dg-final { scan-assembler-times {(?n)shld[ql]?[\t ]*\$2} 2 { target { !
ia32 } } } } */
+/* { dg-additional-options "-mno-sse -mno-mmx" { target ia32 } } */
+/* { dg-final { scan-assembler-times {(?n)shrd[ql]?[\t ]*\$2} 4 } } */
+/* { dg-final { scan-assembler-times {(?n)shld[ql]?[\t ]*\$2} 2 } } */
typedef unsigned long long u64;
typedef unsigned int u32;
