https://gcc.gnu.org/g:2631ac38d9b2a9def13a04c1e1fefb3871e420ab
commit r14-11583-g2631ac38d9b2a9def13a04c1e1fefb3871e420ab
Author: Jin Ma <ji...@linux.alibaba.com>
Date: Tue Jan 21 10:46:37 2025 -0700
RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not
get a non-zero immediate
Although we have handled the vl of XTheadVector correctly in the
expand phase and predicates, the results show that the work is
still insufficient.
In the curr_insn_transform function, the insn is transformed from:
(insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128]
A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(reg:DI 209)
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 143 [ _xx ])
(mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128] A32])))
(expr_list:REG_DEAD (reg/v:RVVM8SF 143 [ _xx ])
(nil)))
to
(insn 69 284 225 11 (set (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ]
[218]) [0 S[128, 128] A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(const_int 1 [0x1])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 104 v8 [orig:143 _xx ] [143])
(mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0 S[128,
128] A32])))
(nil))
Looking at the log for the reload pass, it is found that "Changing pseudo
209 in
operand 3 of insn 69 on equiv 0x1".
It converts the vl operand in insn from the expected register(reg:DI 209)
to the
constant 1(const_int 1 [0x1]).
This conversion occurs because, although the predicate for the vl operand is
restricted by "vector_length_operand" in the pattern, the constraint is
still
"rK", which allows the transformation.
The issue is that changing the "rK" constraint to "rJ" for the constraint
of vl
operand in the pattern would prevent this conversion, But unfortunately
this will
conflict with RVV (RISC-V Vector Extension).
Based on the review's recommendations, the best solution for now is to
create
a new constraint to distinguish between RVV and XTheadVector, which is
exactly
what this patch does.
PR target/116593
gcc/ChangeLog:
* config/riscv/constraints.md (vl): New.
* config/riscv/thead-vector.md: Replacing rK with rvl.
* config/riscv/vector.md: Likewise.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/rvv.exp: Enable testsuite of XTheadVector.
* g++.target/riscv/rvv/xtheadvector/pr116593.C: New test.
(cherry picked from commit 3024b12f2cde5db3bf52b49b07e32ef3065929fb)
Diff:
---
gcc/config/riscv/constraints.md | 6 +
gcc/config/riscv/thead-vector.md | 18 +-
gcc/config/riscv/vector.md | 500 ++++++++++-----------
gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 3 +
.../g++.target/riscv/rvv/xtheadvector/pr116593.C | 47 ++
5 files changed, 315 insertions(+), 259 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index a590df545d7d..a03a1d755051 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -188,6 +188,12 @@
(and (match_code "const_vector")
(match_test "riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)")))
+(define_constraint "vl"
+ "A uimm5 for Vector or zero for XTheadVector."
+ (and (match_code "const_int")
+ (ior (match_test "!TARGET_XTHEADVECTOR && satisfies_constraint_K (op)")
+ (match_test "TARGET_XTHEADVECTOR && satisfies_constraint_J (op)"))))
+
(define_constraint "Wc0"
"@internal
A constraint that matches a vector of immediate all zeros."
diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md
index 5fe9ba08c4eb..5a02debdd207 100644
--- a/gcc/config/riscv/thead-vector.md
+++ b/gcc/config/riscv/thead-vector.md
@@ -108,7 +108,7 @@
[(set (match_operand:V_VLS_VT 0 "reg_or_mem_operand" "=vr,vr, m")
(unspec:V_VLS_VT
[(match_operand:V_VLS_VT 1 "reg_or_mem_operand" " vr, m,vr")
- (match_operand 2 "vector_length_operand" " rK, rK, rK")
+ (match_operand 2 "vector_length_operand" "rvl,rvl,rvl")
(match_operand 3 "const_1_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)]
@@ -133,7 +133,7 @@
[(set (match_operand:VB 0 "reg_or_mem_operand" "=vr,vr, m")
(unspec:VB
[(match_operand:VB 1 "reg_or_mem_operand" " vr, m,vr")
- (match_operand 2 "vector_length_operand" " rK, rK, rK")
+ (match_operand 2 "vector_length_operand" "rvl,rvl,rvl")
(match_operand 3 "const_1_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)]
@@ -161,7 +161,7 @@
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1,
Wc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl, rvl,
rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -210,7 +210,7 @@
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1,
vm, vmWc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
@@ -239,7 +239,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSMEM_OP)
@@ -257,7 +257,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 5 "vector_length_operand" " rK, rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
(match_operand 8 "const_int_operand" " i, i, i")
@@ -277,7 +277,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSMEM_OP)
@@ -296,7 +296,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -317,7 +317,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSXMEM_OP)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 327690a71f46..6fd169746934 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1621,7 +1621,7 @@
(define_insn "@vsetvl<mode>"
[(set (match_operand:P 0 "register_operand" "=r")
- (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
+ (unspec:P [(match_operand:P 1 "vector_length_operand" "rvl")
(match_operand 2 "const_int_operand" "i")
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")
@@ -1667,7 +1667,7 @@
;; in vsetvl instruction pattern.
(define_insn "@vsetvl_discard_result<mode>"
[(set (reg:SI VL_REGNUM)
- (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
+ (unspec:SI [(match_operand:P 0 "vector_length_operand" "rvl")
(match_operand 1 "const_int_operand" "i")
(match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
(set (reg:SI VTYPE_REGNUM)
@@ -1689,7 +1689,7 @@
;; such pattern can allow us gain benefits of these optimizations.
(define_insn_and_split "@vsetvl<mode>_no_side_effects"
[(set (match_operand:P 0 "register_operand" "=r")
- (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
+ (unspec:P [(match_operand:P 1 "vector_length_operand" "rvl")
(match_operand 2 "const_int_operand" "i")
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")
@@ -1814,7 +1814,7 @@
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1,
vm, vmWc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
@@ -1845,7 +1845,7 @@
(if_then_else:V
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -1868,7 +1868,7 @@
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1,
Wc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl, rvl,
rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -1894,7 +1894,7 @@
(if_then_else:VB
(unspec:VB
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" "rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -1911,7 +1911,7 @@
[(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
(if_then_else:V_VLS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
@@ -1930,7 +1930,7 @@
[(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSI_QHS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -1982,7 +1982,7 @@
[(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -2002,7 +2002,7 @@
[(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -2101,7 +2101,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,
vm, vm,Wc1,Wc1,Wb1,Wb1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i")
@@ -2162,7 +2162,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1, Wc1,
Wb1, Wb1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl, rvl,
rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i")
@@ -2185,7 +2185,7 @@
(if_then_else:V_VLSF_ZVFHMIN
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" " vm,
vm, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,
rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i,
i, i, i")
(match_operand 6 "const_int_operand" " i,
i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i")
@@ -2208,7 +2208,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand"
"Wc1,Wc1,Wb1,Wb1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i")
@@ -2232,7 +2232,7 @@
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_least_significant_set_mask_operand"
"Wb1, Wb1")
- (match_operand 4 "vector_length_operand" "
rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl, rvl")
(match_operand 5 "const_int_operand" "
i, i")
(match_operand 6 "const_int_operand" "
i, i")
(match_operand 7 "const_int_operand" "
i, i")
@@ -2252,7 +2252,7 @@
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1,
Wc1")
- (match_operand 4 "vector_length_operand" " rK,
rK")
+ (match_operand 4 "vector_length_operand" " rvl,
rvl")
(match_operand 5 "const_int_operand" " i,
i")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
@@ -2277,7 +2277,7 @@
(if_then_else:V
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm,
vmWc1, Wc1, vm")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl, rvl,
rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i, i")
@@ -2303,7 +2303,7 @@
(if_then_else:V
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2332,7 +2332,7 @@
(if_then_else:VINDEXED
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2354,7 +2354,7 @@
(if_then_else:VEEWEXT2
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -2375,7 +2375,7 @@
(if_then_else:VEEWEXT4
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -2396,7 +2396,7 @@
(if_then_else:VEEWEXT8
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -2418,7 +2418,7 @@
(if_then_else:VEEWTRUNC2
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i")
@@ -2439,7 +2439,7 @@
(if_then_else:VEEWTRUNC4
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i")
@@ -2460,7 +2460,7 @@
(if_then_else:VEEWTRUNC8
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i, i")
@@ -2481,7 +2481,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2498,7 +2498,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2515,7 +2515,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2532,7 +2532,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2549,7 +2549,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2566,7 +2566,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2583,7 +2583,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2613,7 +2613,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm,
vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,
rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i, i,
i, i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i, i, i, i, i, i, i")
@@ -2649,7 +2649,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK,
rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i, i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i, i, i, i, i,
i, i")
@@ -2670,7 +2670,7 @@
(if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2691,7 +2691,7 @@
(if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2712,7 +2712,7 @@
(if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2768,7 +2768,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2789,7 +2789,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2844,7 +2844,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2865,7 +2865,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2920,7 +2920,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2941,7 +2941,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2964,7 +2964,7 @@
(if_then_else:VFULLI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2984,7 +2984,7 @@
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3038,7 +3038,7 @@
(if_then_else:VFULLI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3059,7 +3059,7 @@
(if_then_else:VFULLI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3081,7 +3081,7 @@
[(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
(if_then_else:VI
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
@@ -3105,7 +3105,7 @@
[(set (match_operand:VI 0 "register_operand" "=vd,vd")
(if_then_else:VI
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3129,7 +3129,7 @@
[(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
(if_then_else:VI_QHS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3154,7 +3154,7 @@
[(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
(if_then_else:VI_QHS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3212,7 +3212,7 @@
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3237,7 +3237,7 @@
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3296,7 +3296,7 @@
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3321,7 +3321,7 @@
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3351,7 +3351,7 @@
(match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK, rK")
+ [(match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3371,7 +3371,7 @@
(match_operand:VI 2 "register_operand" " vr, 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl,rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3392,7 +3392,7 @@
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3413,7 +3413,7 @@
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3463,7 +3463,7 @@
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3485,7 +3485,7 @@
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3535,7 +3535,7 @@
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3557,7 +3557,7 @@
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3576,7 +3576,7 @@
(match_operand:VI 1 "register_operand" " %0, vr, vr")
(match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK, rK")
+ [(match_operand 3 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 4 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3595,7 +3595,7 @@
(match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
(match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
+ [(match_operand 3 "vector_length_operand" " rvl, rvl, rvl, rvl")
(match_operand 4 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3615,7 +3615,7 @@
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3635,7 +3635,7 @@
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3683,7 +3683,7 @@
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3704,7 +3704,7 @@
(match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3752,7 +3752,7 @@
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3773,7 +3773,7 @@
(match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3797,7 +3797,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -3830,7 +3830,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -3850,7 +3850,7 @@
(if_then_else:VQEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -3870,7 +3870,7 @@
(if_then_else:VOEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -3890,7 +3890,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -3912,7 +3912,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -3935,7 +3935,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -3956,7 +3956,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -3977,7 +3977,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK,rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -3999,7 +3999,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK,rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -4022,7 +4022,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK,rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -4045,7 +4045,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4067,7 +4067,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4091,7 +4091,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK,
rK")
+ (match_operand 4 "vector_length_operand" " rvl,
rvl")
(match_operand 5 "const_int_operand" " i,
i")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
@@ -4127,7 +4127,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,rK,
rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl, rvl, rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
@@ -4149,7 +4149,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 8 "const_int_operand" " i,
i, i, i, i, i")
@@ -4172,7 +4172,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK,
rK, rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 6 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i, i, i")
@@ -4208,7 +4208,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm,
vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i, i, i")
@@ -4237,7 +4237,7 @@
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4258,7 +4258,7 @@
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4312,7 +4312,7 @@
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4333,7 +4333,7 @@
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4388,7 +4388,7 @@
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4409,7 +4409,7 @@
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4431,7 +4431,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4454,7 +4454,7 @@
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4476,7 +4476,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4534,7 +4534,7 @@
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4556,7 +4556,7 @@
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4580,7 +4580,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,rK,
rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl, rvl, rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
@@ -4603,7 +4603,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 8 "const_int_operand" " i,
i, i, i, i, i")
@@ -4650,7 +4650,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4674,7 +4674,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4695,7 +4695,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4732,7 +4732,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4756,7 +4756,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4777,7 +4777,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4815,7 +4815,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4840,7 +4840,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -4862,7 +4862,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -4901,7 +4901,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4926,7 +4926,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -4948,7 +4948,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -5044,7 +5044,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -5068,7 +5068,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -5093,7 +5093,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5115,7 +5115,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5137,7 +5137,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5159,7 +5159,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -5180,7 +5180,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -5206,7 +5206,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5228,7 +5228,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -5250,7 +5250,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -5276,7 +5276,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5298,7 +5298,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -5466,7 +5466,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1,
Wc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK,
rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl,rvl,
rvl")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 9 "const_int_operand" " i, i, i, i, i,
i")
@@ -5494,7 +5494,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5525,7 +5525,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5577,7 +5577,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5609,7 +5609,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5676,7 +5676,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,
Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl,
rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -5709,7 +5709,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,
Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl,
rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -5764,7 +5764,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1,
Wc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK,
rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl,rvl,
rvl")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 9 "const_int_operand" " i, i, i, i, i,
i")
@@ -5792,7 +5792,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5823,7 +5823,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5875,7 +5875,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5907,7 +5907,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -5974,7 +5974,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,
Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl,
rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -6007,7 +6007,7 @@
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,
Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl,
rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -6047,7 +6047,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -6071,7 +6071,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -6096,7 +6096,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -6120,7 +6120,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -6145,7 +6145,7 @@
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -6187,7 +6187,7 @@
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6207,7 +6207,7 @@
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6228,7 +6228,7 @@
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6249,7 +6249,7 @@
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" "rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6270,7 +6270,7 @@
[(and:VB
(match_operand:VB 1 "vector_mask_operand" "vmWc1")
(match_operand:VB 2 "register_operand" " vr"))
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
@@ -6287,7 +6287,7 @@
[(and:VB
(match_operand:VB 1 "vector_mask_operand" "vmWc1")
(match_operand:VB 2 "register_operand" " vr"))
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
@@ -6302,7 +6302,7 @@
(if_then_else:VB
(unspec:VB
[(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -6320,7 +6320,7 @@
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -6339,7 +6339,7 @@
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 3 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 4 "const_int_operand" " i, i, i, i")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
@@ -6367,7 +6367,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6391,7 +6391,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6411,7 +6411,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6432,7 +6432,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6457,7 +6457,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6478,7 +6478,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6500,7 +6500,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6525,7 +6525,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6550,7 +6550,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6570,7 +6570,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6591,7 +6591,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6612,7 +6612,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6665,7 +6665,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1,
Wc1")
- (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK,
rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl,rvl,
rvl")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 9 "const_int_operand" " i, i, i, i, i,
i")
@@ -6697,7 +6697,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6732,7 +6732,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6790,7 +6790,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6826,7 +6826,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6887,7 +6887,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1,
Wc1")
- (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK,
rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl,rvl,
rvl")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i")
(match_operand 9 "const_int_operand" " i, i, i, i, i,
i")
@@ -6920,7 +6920,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6956,7 +6956,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -7016,7 +7016,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -7053,7 +7053,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,
Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand" "rvl, rvl,rvl,
rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -7101,7 +7101,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7128,7 +7128,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7151,7 +7151,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7170,7 +7170,7 @@
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7193,7 +7193,7 @@
(if_then_else:<VCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7221,7 +7221,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7247,7 +7247,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7274,7 +7274,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7299,7 +7299,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7324,7 +7324,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -7357,7 +7357,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7385,7 +7385,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7414,7 +7414,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7443,7 +7443,7 @@
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7498,7 +7498,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -7518,7 +7518,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7542,7 +7542,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -7580,7 +7580,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7605,7 +7605,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -7627,7 +7627,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -7666,7 +7666,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7691,7 +7691,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -7713,7 +7713,7 @@
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -7740,7 +7740,7 @@
[(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSF
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -7768,7 +7768,7 @@
(if_then_else:<VCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7791,7 +7791,7 @@
(if_then_else:<VCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7810,7 +7810,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7840,7 +7840,7 @@
(if_then_else:VWCONVERTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7863,7 +7863,7 @@
(if_then_else:VWCONVERTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7882,7 +7882,7 @@
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7901,7 +7901,7 @@
(if_then_else:VWEXTF_ZVFHMIN
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7927,7 +7927,7 @@
(if_then_else:<VNCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
@@ -7951,7 +7951,7 @@
(if_then_else:<VNCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl,
rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i, i, i,
i, i")
@@ -7970,7 +7970,7 @@
(if_then_else:<VNCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl,
rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i, i, i,
i, i")
@@ -7994,7 +7994,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
@@ -8018,7 +8018,7 @@
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
@@ -8054,7 +8054,7 @@
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(reg:SI VL_REGNUM)
@@ -8076,7 +8076,7 @@
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -8097,7 +8097,7 @@
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(reg:SI VL_REGNUM)
@@ -8119,7 +8119,7 @@
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -8140,7 +8140,7 @@
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(reg:SI VL_REGNUM)
@@ -8162,7 +8162,7 @@
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -8183,7 +8183,7 @@
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -8209,7 +8209,7 @@
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -8234,7 +8234,7 @@
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -8260,7 +8260,7 @@
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -8388,7 +8388,7 @@
(unspec:V_VLS
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8408,7 +8408,7 @@
(unspec:V_VLSI_QHS
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8452,7 +8452,7 @@
(unspec:V_VLSI_D
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8471,7 +8471,7 @@
(unspec:V_VLSI_D
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8492,7 +8492,7 @@
(unspec:V_VLSF
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8512,7 +8512,7 @@
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8532,7 +8532,7 @@
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8553,7 +8553,7 @@
(if_then_else:VEI16
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8574,7 +8574,7 @@
(unspec:V_VLS
[(unspec:<VM>
[(match_operand:<VM> 3 "register_operand" " vm, vm")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -8614,7 +8614,7 @@
(if_then_else:V
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1,
Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl, rvl,
rvl")
(match_operand 5 "const_int_operand" " i, i, i,
i")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
@@ -8652,7 +8652,7 @@
(if_then_else:VT
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 4 "vector_length_operand" " rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
@@ -8672,7 +8672,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8689,7 +8689,7 @@
(if_then_else:VT
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 5 "vector_length_operand" " rK, rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
(match_operand 8 "const_int_operand" " i, i, i")
@@ -8710,7 +8710,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8728,7 +8728,7 @@
(if_then_else:VT
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 4 "vector_length_operand" " rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
@@ -8759,7 +8759,7 @@
(if_then_else:V1T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8780,7 +8780,7 @@
(if_then_else:V2T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8801,7 +8801,7 @@
(if_then_else:V4T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8822,7 +8822,7 @@
(if_then_else:V8T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8843,7 +8843,7 @@
(if_then_else:V16T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8864,7 +8864,7 @@
(if_then_else:V32T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8885,7 +8885,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8902,7 +8902,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8919,7 +8919,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8936,7 +8936,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8953,7 +8953,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8970,7 +8970,7 @@
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index c42998e0f8a5..055451a2556d 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -45,5 +45,8 @@ dg-runtest [lsort [glob -nocomplain
$srcdir/$subdir/base/*.C]] \
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.C]] \
+ "" $CFLAGS
+
# All done.
dg-finish
diff --git a/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
b/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
new file mode 100644
index 000000000000..cef5bec13e34
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
@@ -0,0 +1,47 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target {
rv32 } } } */
+/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target {
rv64 } } } */
+
+#include <math.h>
+#include <riscv_vector.h>
+#include <vector>
+
+static
+vfloat32m8_t atan2_ps (vfloat32m8_t a, vfloat32m8_t b, size_t vl)
+{
+ std::vector<float> tmpx (vl);
+ std::vector<float> tmpy (vl);
+ __riscv_vse32_v_f32m8 (tmpx.data (), a, vl);
+ __riscv_vse32_v_f32m8 (tmpy.data (), b, vl);
+ for (size_t i = 0; i < vl; i++)
+ {
+ tmpx[i] = atan2 (tmpx[i], tmpy[i]);
+ }
+ return __riscv_vle32_v_f32m8 (tmpx.data (), vl);
+}
+
+void
+atan2 (const float *x, const float *y, float *out, int size, int ch)
+{
+ for (int i = 0; i < ch; i++)
+ {
+ const float *xx = x + size * i;
+ const float *yy = y + size * i;
+ float *zz = out + size * i;
+
+ int n = size;
+ while (n > 0)
+ {
+ size_t vl = __riscv_vsetvl_e32m8 (n);
+ vfloat32m8_t _xx = __riscv_vle32_v_f32m8 (xx, vl);
+ vfloat32m8_t _yy = __riscv_vle32_v_f32m8 (yy, vl);
+ vfloat32m8_t _zz = atan2_ps (_xx, _yy, vl);
+ __riscv_vse32_v_f32m8 (zz, _zz, vl);
+ n -= vl;
+ xx += vl;
+ yy += vl;
+ zz += vl;
+ }
+ }
+}
