[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:c118441b67c334fbb810bb6ffece8940706b75e0

commit c118441b67c334fbb810bb6ffece8940706b75e0
Author: Pan Li <pan2...@intel.com>
Date:   Thu May 8 11:25:04 2025 +0800

    RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR 
cost 2
    
    Add asm dump check and for vec_duplicate + vadd.vv combine case 1 to vadd.vx
    with the cost of GR2VR is 2.  The testcases is not that tidy according
    to the result, but we will continue tuning the cost model for this.
    
    The below test suites are passed for this patch.
    * The rv64gcv fully regression test.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c: New test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c: New test.
    
    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 8dba9c7ec97ef6e5e891c77a0f0d536860172beb)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c  | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c | 9 +++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c  | 8 ++++++++
 8 files changed, 65 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c
new file mode 100644
index 000000000000..d80f0c07d55d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c
new file mode 100644
index 000000000000..99f6614eb7e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c
new file mode 100644
index 000000000000..ab06c51914ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c
new file mode 100644
index 000000000000..7ead9d09b793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c
new file mode 100644
index 000000000000..79b754b934ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c
@@ -0,0 +1,9 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c
new file mode 100644
index 000000000000..2f70dcd11977
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c
new file mode 100644
index 000000000000..8094a2cc7fb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c
new file mode 100644
index 000000000000..56d040b2f862
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */