[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34f2ac, just the RISC-V backend bits.

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:84adfa2f4d281c7ae14c52d8b3ee92e7544afdbe

commit 84adfa2f4d281c7ae14c52d8b3ee92e7544afdbe
Author: Jeff Law <j...@ventanamicro.com>
Date:   Fri May 16 11:27:25 2025 -0600

    Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34f2ac, just the 
RISC-V backend bits.
    
    commit 4dd13988c93c24ba3605f4b9cafc97515c34f2ac
    Author: Richard Sandiford <richard.sandif...@arm.com>
    Date:   Fri May 16 13:24:01 2025 +0100
    
        Automatic replacement of get_insns/end_sequence pairs
    
        This is the result of using a regexp to replace instances of:
    
          <stuff> = get_insns ();
          end_sequence ();
    
        with:
    
          <stuff> = end_sequence ();
    
        where the indentation is the same for both lines, and where there
        might be blank lines inbetween.

Diff:
---
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +--
 gcc/config/riscv/riscv-vsetvl.cc          |  6 ++----
 gcc/config/riscv/riscv.cc                 | 10 +++-------
 3 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc 
b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 60f330e656e9..2e3d9f6a2c3c 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -189,8 +189,7 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block 
bb)
                }
            }
        }
-      rtx_insn *seq = get_insns ();
-      end_sequence ();
+      rtx_insn *seq = end_sequence ();
       emit_insn_before (seq, insn);
     }
 }
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index a8c92565541a..4891b6c95e85 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3419,8 +3419,7 @@ pre_vsetvl::emit_vsetvl ()
            }
          start_sequence ();
          insert_vsetvl_insn (EMIT_DIRECT, footer_info);
-         rtx_insn *rinsn = get_insns ();
-         end_sequence ();
+         rtx_insn *rinsn = end_sequence ();
          default_rtl_profile ();
          insert_insn_on_edge (rinsn, eg);
          need_commit = true;
@@ -3451,8 +3450,7 @@ pre_vsetvl::emit_vsetvl ()
       start_sequence ();
 
       insert_vsetvl_insn (EMIT_DIRECT, info);
-      rtx_insn *rinsn = get_insns ();
-      end_sequence ();
+      rtx_insn *rinsn = end_sequence ();
       default_rtl_profile ();
 
       /* We should not get an abnormal edge here.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b1d44f7539e5..fd51472dbeaa 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2856,9 +2856,7 @@ riscv_call_tls_get_addr (rtx sym, rtx result)
                                         gen_int_mode (RISCV_CC_BASE, SImode)));
   RTL_CONST_CALL_P (insn) = 1;
   use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
-  insn = get_insns ();
-
-  end_sequence ();
+  insn = end_sequence ();
 
   return insn;
 }
@@ -12180,8 +12178,7 @@ riscv_frm_emit_after_bb_end (rtx_insn *cur_insn)
        {
          start_sequence ();
          emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun)));
-         rtx_insn *backup_insn = get_insns ();
-         end_sequence ();
+         rtx_insn *backup_insn = end_sequence ();
 
          insert_insn_on_edge (backup_insn, eg);
        }
@@ -12191,8 +12188,7 @@ riscv_frm_emit_after_bb_end (rtx_insn *cur_insn)
     {
       start_sequence ();
       emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun)));
-      rtx_insn *backup_insn = get_insns ();
-      end_sequence ();
+      rtx_insn *backup_insn = end_sequence ();
 
       insert_insn_end_basic_block (backup_insn, bb);
     }