https://gcc.gnu.org/g:dbc3e4ec82fcfcf17f12065b7b7e71cca3af9c19

commit dbc3e4ec82fcfcf17f12065b7b7e71cca3af9c19
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Tue Jun 10 17:34:06 2025 -0400

    PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
    
    2025-06-10  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/
    
            PR target/117251
            * config/rs6000/fusion.md: Regenerate.
            * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to
            generate vector orc => xor fusion if XXEVAL is supported.

Diff:
---
 gcc/config/rs6000/fusion.md    | 15 +++++++++------
 gcc/config/rs6000/genfusion.pl |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index cb1ad8b4c0cc..3d7e6502b027 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -3071,20 +3071,23 @@
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vorc -> vxor
 (define_insn "*fuse_vorc_vxor"
-  [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
-        (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" 
"v,v,v,v"))
-                          (match_operand:VM 1 "altivec_register_operand" 
"v,v,v,v"))
-                 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
-   (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+  [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+        (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" 
"v,v,v,wa,v"))
+                          (match_operand:VM 1 "vector_fusion_operand" 
"v,v,v,wa,v"))
+                 (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))
+   (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
   "(TARGET_P10_FUSION)"
   "@
    vorc %3,%1,%0\;vxor %3,%3,%2
    vorc %3,%1,%0\;vxor %3,%3,%2
    vorc %3,%1,%0\;vxor %3,%3,%2
+   xxeval %x3,%x2,%x1,%x0,180
    vorc %4,%1,%0\;vxor %3,%4,%2"
   [(set_attr "type" "fused_vector")
    (set_attr "cost" "6")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "prefixed" "*,*,*,yes,*")
+   (set_attr "isa" "*,*,*,xxeval,*")])
 
 ;; logical-logical fusion pattern generated by gen_logical_addsubf
 ;; vector vxor -> vxor
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 9400aed267a6..15f931baad33 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -244,6 +244,7 @@ sub gen_logical_addsubf
       "vxor_vnor"   => 144,
       "veqv_vxor"   => 150,
       "veqv_vor"    => 159,
+      "vorc_vxor"   => 180,
     );
 
     KIND: foreach $kind ('scalar','vector') {

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