https://gcc.gnu.org/g:f864fc36fe0db4ca330e0f676937ae30d83aa745
commit r16-3393-gf864fc36fe0db4ca330e0f676937ae30d83aa745
Author: Paul-Antoine Arras <par...@baylibre.com>
Date: Tue Aug 26 06:16:04 2025 -0600
[PATCH] RISC-V: Add pattern for vector-scalar single-width floating-point
multiply
This pattern enables the combine pass (or late-combine, depending on the
case)
to merge a vec_duplicate into a mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfmul.vv v1,v1,v2
After, we get only one:
vfmul.vf v2,v2,fa0
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfmul_vf_<mode>): Add new pattern to
combine vec_duplicate + vfmul.vv into vfmul.vf.
* config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS
modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmul.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: Adjust
scan
dump.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: Likewise.
Diff:
---
gcc/config/riscv/autovec-opt.md | 19 +++
gcc/config/riscv/vector.md | 12 +-
.../riscv/rvv/autovec/vls/floating-point-mul-2.c | 2 +-
.../riscv/rvv/autovec/vls/floating-point-mul-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 3 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 3 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 3 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h | 64 +++++++++
.../riscv/rvv/autovec/vx_vf/vf_binop_data.h | 157 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vf_binop_run.h | 42 ++++++
.../riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c | 19 +++
.../riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c | 15 ++
.../riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c | 15 ++
22 files changed, 365 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 0e37a3bf390a..e9d923c16a20 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2027,3 +2027,22 @@
}
[(set_attr "type" "vfwmuladd")]
)
+
+;; vfmul.vf
+(define_insn_and_split "*vfmul_vf_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (mult:V_VLSF
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))
+ (match_operand:V_VLSF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (MULT, <MODE>mode),
+ riscv_vector::BINARY_OP_FRM_DYN, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfmuladd")]
+)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index c11d61a5cd23..19aec173ad05 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6370,8 +6370,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
@@ -6382,11 +6382,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (commutative_float_binop:VF
- (vec_duplicate:VF
+ (commutative_float_binop:V_VLSF
+ (vec_duplicate:V_VLSF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
0")))]
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
index 297f049795b1..3af7e64aecd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
@@ -39,5 +39,5 @@ DEF_OP_VX (mul, 128, double, *)
DEF_OP_VX (mul, 256, double, *)
DEF_OP_VX (mul, 512, double, *)
-/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times
{vfmul\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
index f49bf28f0ff0..f1d594416b04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
@@ -39,5 +39,5 @@ DEF_OP_VI_15 (mul, 128, double, *)
DEF_OP_VI_15 (mul, 256, double, *)
DEF_OP_VI_15 (mul, 512, double, *)
-/* { dg-final { scan-assembler-times
{vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times
{vfmul\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index 811f26c156a9..24433da6c43c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -2,6 +2,7 @@
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */
#include "vf_mulop.h"
+#include "vf_binop.h"
DEF_VF_MULOP_CASE_0 (_Float16, +, +, add)
DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub)
@@ -15,6 +16,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
+DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -28,3 +30,4 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index ca82ead9d28c..913657fac2f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -2,6 +2,7 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */
#include "vf_mulop.h"
+#include "vf_binop.h"
DEF_VF_MULOP_CASE_0 (float, +, +, add)
DEF_VF_MULOP_CASE_0 (float, -, +, sub)
@@ -15,6 +16,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
+DEF_VF_BINOP_CASE_0 (float, *, mul)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -28,3 +30,4 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 4de038c62994..742dc91c2afb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -2,6 +2,7 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */
#include "vf_mulop.h"
+#include "vf_binop.h"
DEF_VF_MULOP_CASE_0 (double, +, +, add)
DEF_VF_MULOP_CASE_0 (double, -, +, sub)
@@ -11,6 +12,7 @@ DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc)
DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac)
DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
+DEF_VF_BINOP_CASE_0 (double, *, mul)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -20,3 +22,4 @@ DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 3a39303f9422..99bd6b78b8fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -15,5 +15,6 @@
/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */
-/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */
+/* { dg-final { scan-assembler-times {vfmv.v.f} 13 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index b4618bae70eb..b11e966d64bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -15,5 +15,6 @@
/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */
-/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */
+/* { dg-final { scan-assembler-times {vfmv.v.f} 13 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index a2ac67e4a8d9..89a105931616 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -11,3 +11,4 @@
/* { dg-final { scan-assembler-not {vfmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfmul.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index d50f376c1f25..14ee897ac3cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -2,6 +2,7 @@
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */
#include "vf_mulop.h"
+#include "vf_binop.h"
DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X128)
DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X128)
@@ -15,6 +16,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
+DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -28,3 +30,4 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
/* { dg-final { scan-assembler {vfwmsac.vf} } } */
/* { dg-final { scan-assembler {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
+/* { dg-final { scan-assembler {vfmul.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index fe68d6ea0179..d579ee583589 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -2,6 +2,7 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */
#include "vf_mulop.h"
+#include "vf_binop.h"
DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X128)
DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X128)
@@ -15,6 +16,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
+DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -28,3 +30,4 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
/* { dg-final { scan-assembler {vfwmsac.vf} } } */
/* { dg-final { scan-assembler {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
+/* { dg-final { scan-assembler {vfmul.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 0b83d969a3a0..6f3340d202e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -2,6 +2,7 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */
#include "vf_mulop.h"
+#include "vf_binop.h"
DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X128)
DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X128)
@@ -11,6 +12,7 @@ DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc,
VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
+DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -20,3 +22,4 @@ DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac,
VF_MULOP_ACC_BODY_X128)
/* { dg-final { scan-assembler {vfmsac.vf} } } */
/* { dg-final { scan-assembler {vfnmacc.vf} } } */
/* { dg-final { scan-assembler {vfnmsac.vf} } } */
+/* { dg-final { scan-assembler {vfmul.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index 559df6c7976b..0fb1efd2d4b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -15,4 +15,5 @@
/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler {fcvt.s.h} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index 03f9c5a3d864..0de8064d288f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -15,4 +15,5 @@
/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler {fcvt.d.s} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index d71bdde26afe..75822028a0ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -11,3 +11,4 @@
/* { dg-final { scan-assembler-not {vfmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfmul.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
new file mode 100644
index 000000000000..abe77a080d4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
@@ -0,0 +1,64 @@
+#ifndef HAVE_DEFINED_VF_BINOP_H
+#define HAVE_DEFINED_VF_BINOP_H
+
+#include <stdint.h>
+
+#define DEF_VF_BINOP_CASE_0(T, OP, NAME)
\
+ void test_vf_binop_##NAME##_##T##_case_0 (T *restrict out, T *restrict in,
\
+ T f, unsigned n) \
+ {
\
+ for (unsigned i = 0; i < n; i++)
\
+ out[i] = f OP in[i];
\
+ }
+#define DEF_VF_BINOP_CASE_0_WRAP(T, OP, NAME) DEF_VF_BINOP_CASE_0 (T, OP, NAME)
+#define RUN_VF_BINOP_CASE_0(T, NAME, out, in, f, n)
\
+ test_vf_binop_##NAME##_##T##_case_0 (out, in, f, n)
+#define RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n)
\
+ RUN_VF_BINOP_CASE_0 (T, NAME, out, in, f, n)
+
+#define VF_BINOP_BODY(op)
\
+ out[k + 0] = tmp op in[k + 0];
\
+ out[k + 1] = tmp op in[k + 1];
\
+ k += 2;
+
+#define VF_BINOP_BODY_X4(op)
\
+ VF_BINOP_BODY (op)
\
+ VF_BINOP_BODY (op)
+
+#define VF_BINOP_BODY_X8(op)
\
+ VF_BINOP_BODY_X4 (op)
\
+ VF_BINOP_BODY_X4 (op)
+
+#define VF_BINOP_BODY_X16(op)
\
+ VF_BINOP_BODY_X8 (op)
\
+ VF_BINOP_BODY_X8 (op)
+
+#define VF_BINOP_BODY_X32(op)
\
+ VF_BINOP_BODY_X16 (op)
\
+ VF_BINOP_BODY_X16 (op)
+
+#define VF_BINOP_BODY_X64(op)
\
+ VF_BINOP_BODY_X32 (op)
\
+ VF_BINOP_BODY_X32 (op)
+
+#define VF_BINOP_BODY_X128(op)
\
+ VF_BINOP_BODY_X64 (op)
\
+ VF_BINOP_BODY_X64 (op)
+
+#define DEF_VF_BINOP_CASE_1(T, OP, NAME, BODY)
\
+ void test_vf_binop_##NAME##_##T##_case_1 (T *restrict out, T *restrict in,
\
+ T f, unsigned n) \
+ {
\
+ unsigned k = 0;
\
+ T tmp = f + 3.45;
\
+
\
+ while (k < n)
\
+ {
\
+ tmp = tmp * 0x3.fp2; \
+ BODY (OP) \
+ }
\
+ }
+#define DEF_VF_BINOP_CASE_1_WRAP(T, OP, NAME, BODY)
\
+ DEF_VF_BINOP_CASE_1 (T, OP, NAME, BODY)
+
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
new file mode 100644
index 000000000000..58cfc996d468
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -0,0 +1,157 @@
+#ifndef HAVE_DEFINED_VF_BINOP_DATA_H
+#define HAVE_DEFINED_VF_BINOP_DATA_H
+
+#define N 16
+
+#define TEST_BINOP_DATA(T, NAME) test_##T##_##NAME##_data
+#define TEST_BINOP_DATA_WRAP(T, NAME) TEST_BINOP_DATA(T, NAME)
+
+
+_Float16 TEST_BINOP_DATA(_Float16, mul)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0f16 },
+ {
+ 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
0x1.8fc0000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
0x1.a4c0000000000p+5f16,
+ 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
0x1.6f80000000000p+4f16,
+ },
+ {
+ 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
0x1.8fc0000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
0x1.a4c0000000000p+5f16,
+ 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
0x1.6f80000000000p+4f16,
+ },
+ },
+ {
+ { 0x1.0000000000000p+7f16 },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
-0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
0x1.c300000000000p+6f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
-0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
-0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ {
+ -0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16,
-0x1.53c0000000000p+12f16, -0x1.53c0000000000p+12f16,
+ 0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16,
0x1.c300000000000p+13f16, 0x1.c300000000000p+13f16,
+ -0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16,
-0x1.ffc0000000000p+14f16, -0x1.ffc0000000000p+14f16,
+ -0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16,
-0x1.94c0000000000p+13f16, -0x1.94c0000000000p+13f16,
+ },
+ },
+ {
+ { -0x1.fc00000000000p+6f16 },
+ {
+ -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
-0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+ -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
-0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+ 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
0x1.96c0000000000p+4f16,
+ -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
-0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+ },
+ {
+ 0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16,
0x1.0400000000000p+12f16, 0x1.0400000000000p+12f16,
+ 0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16,
0x1.e180000000000p+14f16, 0x1.e180000000000p+14f16,
+ -0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16,
-0x1.9380000000000p+11f16, -0x1.9380000000000p+11f16,
+ 0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16,
0x1.06c0000000000p+12f16, 0x1.06c0000000000p+12f16,
+ },
+ },
+};
+
+float TEST_BINOP_DATA(float, mul)[][4][N] =
+{
+ {
+ { 0x1.4000000000000p+3f },
+ {
+ 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f, 0x1.a022ea0000000p+60f,
0x1.a022ea0000000p+60f,
+ 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f, 0x1.aa49660000000p+62f,
0x1.aa49660000000p+62f,
+ -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f, -0x1.ac3a220000000p+62f,
-0x1.ac3a220000000p+62f,
+ 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f, 0x1.62cc880000000p+58f,
0x1.62cc880000000p+58f,
+ },
+ {
+ 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f, 0x1.0415d20000000p+64f,
0x1.0415d20000000p+64f,
+ 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f, 0x1.0a6de00000000p+66f,
0x1.0a6de00000000p+66f,
+ -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f, -0x1.0ba4540000000p+66f,
-0x1.0ba4540000000p+66f,
+ 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f, 0x1.bb7faa0000000p+61f,
0x1.bb7faa0000000p+61f,
+ },
+ },
+ {
+ { 0x1.d1a94a0000000p+39f },
+ {
+ 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f,
0x1.de3d100000000p+63f,
+ 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f,
0x1.82ed340000000p+60f,
+ 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f,
0x1.e4075c0000000p+63f,
+ 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f,
0x1.b7f1700000000p+62f,
+ },
+ {
+ 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f, 0x1.b2f4960000000p+103f,
0x1.b2f4960000000p+103f,
+ 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f, 0x1.5fe85c0000000p+100f,
0x1.5fe85c0000000p+100f,
+ 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f, 0x1.b838ba0000000p+103f,
0x1.b838ba0000000p+103f,
+ 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f, 0x1.90203e0000000p+102f,
0x1.90203e0000000p+102f,
+ },
+ },
+ {
+ { 0x1.0c6f7a0000000p-20f },
+ {
+ 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f, 0x1.de3d100000000p+63f,
0x1.de3d100000000p+63f,
+ 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f, 0x1.82ed340000000p+60f,
0x1.82ed340000000p+60f,
+ 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f, 0x1.e4075c0000000p+63f,
0x1.e4075c0000000p+63f,
+ 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f, 0x1.b7f1700000000p+62f,
0x1.b7f1700000000p+62f,
+ },
+ {
+ 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f, 0x1.f5782e0000000p+43f,
0x1.f5782e0000000p+43f,
+ 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f, 0x1.95b8ce0000000p+40f,
0x1.95b8ce0000000p+40f,
+ 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f, 0x1.fb8a7a0000000p+43f,
0x1.fb8a7a0000000p+43f,
+ 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f, 0x1.cd50560000000p+42f,
0x1.cd50560000000p+42f,
+ },
+ },
+};
+
+double TEST_BINOP_DATA(double, mul)[][4][N] =
+{
+ {
+ { 0x1.0e15635000000p+40 },
+ {
+ -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511, -0x1.1cadd278efdbap+511,
-0x1.1cadd278efdbap+511,
+ 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511, 0x1.7ba13fea68f33p+511,
0x1.7ba13fea68f33p+511,
+ -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511, -0x1.2c51d0517111ep+511,
-0x1.2c51d0517111ep+511,
+ 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511, 0x1.aca8567d5e741p+511,
0x1.aca8567d5e741p+511,
+ },
+ {
+ -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551, -0x1.2c571cadff9bep+551,
-0x1.2c571cadff9bep+551,
+ 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551, 0x1.9083c8e97706cp+551,
0x1.9083c8e97706cp+551,
+ -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551, -0x1.3cd760ed790fcp+551,
-0x1.3cd760ed790fcp+551,
+ 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551, 0x1.c43d5b525ff4bp+551,
0x1.c43d5b525ff4bp+551,
+ },
+ },
+ {
+ { -0x1.34be569fb0edfp+79 },
+ {
+ 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511, 0x1.9249ee7946e55p+511,
0x1.9249ee7946e55p+511,
+ -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510, -0x1.581af8ca64584p+510,
-0x1.581af8ca64584p+510,
+ 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511, 0x1.48f04988397e9p+511,
0x1.48f04988397e9p+511,
+ -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511, -0x1.d54d7ad0a0415p+511,
-0x1.d54d7ad0a0415p+511,
+ },
+ {
+ -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590, -0x1.e52c0de8af5f2p+590,
-0x1.e52c0de8af5f2p+590,
+ 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589, 0x1.9f004bc7dd179p+589,
0x1.9f004bc7dd179p+589,
+ -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590, -0x1.8cb5aa1c618f5p+590,
-0x1.8cb5aa1c618f5p+590,
+ 0x1.1aff130877303p+591, 0x1.1aff130877303p+591, 0x1.1aff130877303p+591,
0x1.1aff130877303p+591,
+ },
+ },
+ {
+ { 0x1.5aac1aa995dfbp-511 },
+ {
+ -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511, -0x1.b1dc3d62e68d9p+511,
-0x1.b1dc3d62e68d9p+511,
+ 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511, 0x1.1ea30828d414dp+511,
0x1.1ea30828d414dp+511,
+ -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508, -0x1.f88d34164cbd0p+508,
-0x1.f88d34164cbd0p+508,
+ 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510, 0x1.c9a81c74a1362p+510,
0x1.c9a81c74a1362p+510,
+ },
+ {
+ -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1, -0x1.25c3ac1058579p+1,
-0x1.25c3ac1058579p+1,
+ 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0, 0x1.84290c6b1a568p+0,
0x1.84290c6b1a568p+0,
+ -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2, -0x1.55a105e8db4bep-2,
-0x1.55a105e8db4bep-2,
+ 0x1.35e071897f867p+0, 0x1.35e071897f867p+0, 0x1.35e071897f867p+0,
0x1.35e071897f867p+0,
+ },
+ },
+};
+
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h
new file mode 100644
index 000000000000..aa70e7c516c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_run.h
@@ -0,0 +1,42 @@
+#ifndef HAVE_DEFINED_VF_BINOP_RUN_H
+#define HAVE_DEFINED_VF_BINOP_RUN_H
+
+#include <math.h>
+#include <stdio.h>
+
+#define TYPE_FABS(x, T)
\
+ (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x))
+
+#define MAX_RELATIVE_DIFF(T)
\
+ (__builtin_types_compatible_p (T, _Float16) ? 0.1f :
\
+ (__builtin_types_compatible_p (T, float) ? 0.01f : 0.01))
+
+int
+main ()
+{
+ unsigned i, k;
+ T out[N];
+
+ for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++)
+ {
+ T f = TEST_DATA[i][0][0];
+ T *in = TEST_DATA[i][1];
+ T *expect = TEST_DATA[i][2];
+
+ TEST_RUN (T, NAME, out, in, f, N);
+
+ for (k = 0; k < N; k++)
+ {
+ T diff = expect[k] - out[k];
+ if (TYPE_FABS (diff, T)
+ > MAX_RELATIVE_DIFF (T) * TYPE_FABS (expect[k], T)) {
+ printf("Mismatch at i=%u, k=%u: expect=%f, out=%f, diff=%f\n", i, k,
(double)expect[k], (double)out[k], (double)diff);
+ __builtin_abort ();
+ }
+ }
+ }
+
+ return 0;
+}
+
+#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c
new file mode 100644
index 000000000000..5d57ec8c090b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f16.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T _Float16
+#define NAME mul
+
+DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME,
out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c
new file mode 100644
index 000000000000..337380a0963b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T float
+#define NAME mul
+
+DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME,
out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c
new file mode 100644
index 000000000000..337380a0963b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmul-run-1-f64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T float
+#define NAME mul
+
+DEF_VF_BINOP_CASE_0_WRAP (T, *, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME,
out, in, f, n)
+
+#include "vf_binop_run.h"
