https://gcc.gnu.org/g:7c2ab5865cacc4fdc1d383156e539b3960face67
commit r16-3395-g7c2ab5865cacc4fdc1d383156e539b3960face67
Author: Paul-Antoine Arras <par...@baylibre.com>
Date: Tue Aug 26 06:19:08 2025 -0600
[PATCH] RISC-V: Add pattern for reverse floating-point divide
This pattern enables the combine pass (or late-combine, depending on the
case)
to merge a vec_duplicate into a div RTL instruction. The vec_duplicate is
the
dividend operand.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfdiv.vv v1,v2,v1
After, we get only one:
vfrdiv.vf v1,v1,fa0
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfrdiv_vf_<mode>): Add new pattern
to
combine vec_duplicate + vfdiv.vv into vfrdiv.vf.
* config/riscv/vector.md (@pred_<optab><mode>_reverse_scalar):
Allow VLS
modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfrdiv.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add support for
reverse
variants.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
reverse variants.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c: New
test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c: New
test.
Diff:
---
gcc/config/riscv/autovec-opt.md | 19 +++
gcc/config/riscv/vector.md | 12 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 3 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 3 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 3 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h | 67 +++++++++-
.../riscv/rvv/autovec/vx_vf/vf_binop_data.h | 147 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c | 19 +++
.../riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c | 19 +++
.../riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c | 19 +++
19 files changed, 313 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index e9d923c16a20..29bdfc3d90fc 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2046,3 +2046,22 @@
}
[(set_attr "type" "vfmuladd")]
)
+
+;; vfrdiv.vf
+(define_insn_and_split "*vfrdiv_vf_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (div:V_VLSF
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))
+ (match_operand:V_VLSF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_reverse_scalar (DIV,
<MODE>mode),
+ riscv_vector::BINARY_OP_FRM_DYN, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfmuladd")]
+)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 19aec173ad05..e7ffeeb9cd64 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6463,8 +6463,8 @@
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
@@ -6475,11 +6475,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (non_commutative_float_binop:VF
- (vec_duplicate:VF
+ (non_commutative_float_binop:V_VLSF
+ (vec_duplicate:V_VLSF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index 24433da6c43c..bbbbc52a7811 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
+DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -30,4 +31,4 @@ DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
-/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index 913657fac2f5..912c037126d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
DEF_VF_BINOP_CASE_0 (float, *, mul)
+DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -31,3 +32,4 @@ DEF_VF_BINOP_CASE_0 (float, *, mul)
/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 742dc91c2afb..1664ac7dbce1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -13,6 +13,7 @@ DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac)
DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
DEF_VF_BINOP_CASE_0 (double, *, mul)
+DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -23,3 +24,4 @@ DEF_VF_BINOP_CASE_0 (double, *, mul)
/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 99bd6b78b8fa..7d251c032b49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -16,5 +16,6 @@
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */
-/* { dg-final { scan-assembler-times {vfmv.v.f} 13 } } */
+/* { dg-final { scan-assembler-times {vfmv.v.f} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index b11e966d64bb..10aac1f87455 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -16,5 +16,6 @@
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */
-/* { dg-final { scan-assembler-times {vfmv.v.f} 13 } } */
+/* { dg-final { scan-assembler-times {vfmv.v.f} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index 89a105931616..b10261f077d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -12,3 +12,4 @@
/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 14ee897ac3cd..09940e9af4aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -31,3 +32,4 @@ DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
/* { dg-final { scan-assembler {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
+/* { dg-final { scan-assembler {vfrdiv.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index d579ee583589..42adaefe0e7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -31,3 +32,4 @@ DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
/* { dg-final { scan-assembler {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
+/* { dg-final { scan-assembler {vfrdiv.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 6f3340d202e0..021296984bb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -13,6 +13,7 @@ DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac,
VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -23,3 +24,4 @@ DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
/* { dg-final { scan-assembler {vfnmacc.vf} } } */
/* { dg-final { scan-assembler {vfnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
+/* { dg-final { scan-assembler {vfrdiv.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index 0fb1efd2d4b5..b6ad62cdb40a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -16,4 +16,5 @@
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {fcvt.s.h} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index 0de8064d288f..14843d1bb7a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -16,4 +16,5 @@
/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {fcvt.d.s} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index 75822028a0ef..7d6752573e07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -12,3 +12,4 @@
/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
index abe77a080d4f..b43b7dc5a97d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
@@ -8,7 +8,7 @@
T f, unsigned n) \
{
\
for (unsigned i = 0; i < n; i++)
\
- out[i] = f OP in[i];
\
+ out[i] = in[i] OP f;
\
}
#define DEF_VF_BINOP_CASE_0_WRAP(T, OP, NAME) DEF_VF_BINOP_CASE_0 (T, OP, NAME)
#define RUN_VF_BINOP_CASE_0(T, NAME, out, in, f, n)
\
@@ -16,9 +16,24 @@
#define RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n)
\
RUN_VF_BINOP_CASE_0 (T, NAME, out, in, f, n)
+#define DEF_VF_BINOP_REVERSE_CASE_0(T, OP, NAME)
\
+ void test_vf_binop_reverse_##NAME##_##T##_case_0 (T *restrict out,
\
+ T *restrict in, T f, \
+ unsigned n) \
+ {
\
+ for (unsigned i = 0; i < n; i++)
\
+ out[i] = f OP in[i];
\
+ }
+#define DEF_VF_BINOP_REVERSE_CASE_0_WRAP(T, OP, NAME)
\
+ DEF_VF_BINOP_REVERSE_CASE_0 (T, OP, NAME)
+#define RUN_VF_BINOP_REVERSE_CASE_0(T, NAME, out, in, f, n)
\
+ test_vf_binop_reverse_##NAME##_##T##_case_0 (out, in, f, n)
+#define RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n)
\
+ RUN_VF_BINOP_REVERSE_CASE_0 (T, NAME, out, in, f, n)
+
#define VF_BINOP_BODY(op)
\
- out[k + 0] = tmp op in[k + 0];
\
- out[k + 1] = tmp op in[k + 1];
\
+ out[k + 0] = in[k + 0] op tmp;
\
+ out[k + 1] = in[k + 1] op tmp;
\
k += 2;
#define VF_BINOP_BODY_X4(op)
\
@@ -61,4 +76,50 @@
#define DEF_VF_BINOP_CASE_1_WRAP(T, OP, NAME, BODY)
\
DEF_VF_BINOP_CASE_1 (T, OP, NAME, BODY)
+#define VF_BINOP_REVERSE_BODY(op)
\
+ out[k + 0] = tmp op in[k + 0];
\
+ out[k + 1] = tmp op in[k + 1];
\
+ k += 2;
+
+#define VF_BINOP_REVERSE_BODY_X4(op)
\
+ VF_BINOP_REVERSE_BODY (op)
\
+ VF_BINOP_REVERSE_BODY (op)
+
+#define VF_BINOP_REVERSE_BODY_X8(op)
\
+ VF_BINOP_REVERSE_BODY_X4 (op)
\
+ VF_BINOP_REVERSE_BODY_X4 (op)
+
+#define VF_BINOP_REVERSE_BODY_X16(op)
\
+ VF_BINOP_REVERSE_BODY_X8 (op)
\
+ VF_BINOP_REVERSE_BODY_X8 (op)
+
+#define VF_BINOP_REVERSE_BODY_X32(op)
\
+ VF_BINOP_REVERSE_BODY_X16 (op)
\
+ VF_BINOP_REVERSE_BODY_X16 (op)
+
+#define VF_BINOP_REVERSE_BODY_X64(op)
\
+ VF_BINOP_REVERSE_BODY_X32 (op)
\
+ VF_BINOP_REVERSE_BODY_X32 (op)
+
+#define VF_BINOP_REVERSE_BODY_X128(op)
\
+ VF_BINOP_REVERSE_BODY_X64 (op)
\
+ VF_BINOP_REVERSE_BODY_X64 (op)
+
+#define DEF_VF_BINOP_REVERSE_CASE_1(T, OP, NAME, BODY)
\
+ void test_vf_binop_reverse_##NAME##_##T##_case_1 (T *restrict out,
\
+ T *restrict in, T f, \
+ unsigned n) \
+ {
\
+ unsigned k = 0;
\
+ T tmp = f + 3.45;
\
+
\
+ while (k < n)
\
+ {
\
+ tmp = tmp * 0x3.fp2; \
+ BODY (OP) \
+ }
\
+ }
+#define DEF_VF_BINOP_REVERSE_CASE_1_WRAP(T, OP, NAME, BODY)
\
+ DEF_VF_BINOP_REVERSE_CASE_1 (T, OP, NAME, BODY)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
index 58cfc996d468..fb902798bf72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -154,4 +154,151 @@ double TEST_BINOP_DATA(double, mul)[][4][N] =
},
};
+_Float16 TEST_BINOP_DATA(_Float16, rdiv)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0f16 },
+ {
+ 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
0x1.8fc0000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
0x1.a4c0000000000p+5f16,
+ 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
0x1.6f80000000000p+4f16,
+ },
+ {
+ 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16, 0x1.4800000000000p-5f16,
0x1.4800000000000p-5f16,
+ 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16, 0x1.2980000000000p-7f16,
0x1.2980000000000p-7f16,
+ 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16, 0x1.3780000000000p-6f16,
0x1.3780000000000p-6f16,
+ 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16, 0x1.64c0000000000p-5f16,
0x1.64c0000000000p-5f16,
+ },
+ },
+ {
+ { 0x1.0000000000000p+0f16 },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
-0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
0x1.c300000000000p+6f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
-0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
-0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ {
+ -0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16,
-0x1.81c0000000000p-6f16, -0x1.81c0000000000p-6f16,
+ 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16, 0x1.2280000000000p-7f16,
0x1.2280000000000p-7f16,
+ -0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16,
-0x1.0040000000000p-8f16, -0x1.0040000000000p-8f16,
+ -0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16,
-0x1.4400000000000p-7f16, -0x1.4400000000000p-7f16,
+ },
+ },
+ {
+ { 0x1.9000000000000p+6f16 },
+ {
+ -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
-0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+ -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
-0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+ 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
0x1.96c0000000000p+4f16,
+ -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
-0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+ },
+ {
+ -0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16,
-0x1.86c0000000000p+1f16, -0x1.86c0000000000p+1f16,
+ -0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16,
-0x1.a600000000000p-2f16, -0x1.a600000000000p-2f16,
+ 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16, 0x1.f7c0000000000p+1f16,
0x1.f7c0000000000p+1f16,
+ -0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16,
-0x1.82c0000000000p+1f16, -0x1.82c0000000000p+1f16,
+ },
+ },
+};
+
+float TEST_BINOP_DATA(float, rdiv)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0f },
+ {
+ 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
0x1.8fe1540000000p+60f,
+ 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
0x1.b8b5320000000p+62f,
+ 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
0x1.a4eb340000000p+61f,
+ 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
0x1.6faeda0000000p+60f,
+ },
+ {
+ 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f, 0x1.47c7360000000p-61f,
0x1.47c7360000000p-61f,
+ 0x1.2969980000000p-63f, 0x1.2969980000000p-63f, 0x1.2969980000000p-63f,
0x1.2969980000000p-63f,
+ 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f, 0x1.37651e0000000p-62f,
0x1.37651e0000000p-62f,
+ 0x1.647b220000000p-61f, 0x1.647b220000000p-61f, 0x1.647b220000000p-61f,
0x1.647b220000000p-61f,
+ },
+ },
+ {
+ { 0x1.fffffe0000000p+63f },
+ {
+ -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
-0x1.53e0ba0000000p+61f,
+ 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
0x1.c3397c0000000p+62f,
+ -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
-0x1.ffe2020000000p+63f,
+ -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
-0x1.94d2a80000000p+62f,
+ },
+ {
+ -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f, -0x1.81a4f80000000p+2f,
-0x1.81a4f80000000p+2f,
+ 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f, 0x1.227b0a0000000p+1f,
0x1.227b0a0000000p+1f,
+ -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f, -0x1.000efe0000000p+0f,
-0x1.000efe0000000p+0f,
+ -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f, -0x1.43c6b20000000p+1f,
-0x1.43c6b20000000p+1f,
+ },
+ },
+ {
+ { -0x1.d301720000000p+104f },
+ {
+ -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
-0x1.062a340000000p+61f,
+ -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
-0x1.e573960000000p+63f,
+ 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
0x1.96d5c20000000p+60f,
+ -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
-0x1.08eb620000000p+61f,
+ },
+ {
+ 0x1.c806200000000p+43f, 0x1.c806200000000p+43f, 0x1.c806200000000p+43f,
0x1.c806200000000p+43f,
+ 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f, 0x1.ec8b9e0000000p+40f,
0x1.ec8b9e0000000p+40f,
+ -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f, -0x1.25dcbc0000000p+44f,
-0x1.25dcbc0000000p+44f,
+ 0x1.c348400000000p+43f, 0x1.c348400000000p+43f, 0x1.c348400000000p+43f,
0x1.c348400000000p+43f,
+ },
+ },
+};
+
+double TEST_BINOP_DATA(double, rdiv)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0 },
+ {
+ 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
0x1.8fe1565f12a78p+508,
+ 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
0x1.b8b533d821ccap+510,
+ 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
0x1.a4eb35b744a54p+509,
+ 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
0x1.6faedb6395f48p+508,
+ },
+ {
+ 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509, 0x1.47c734d265b62p-509,
0x1.47c734d265b62p-509,
+ 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511, 0x1.296997569d3cdp-511,
0x1.296997569d3cdp-511,
+ 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510, 0x1.37651dc4c34fcp-510,
0x1.37651dc4c34fcp-510,
+ 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509, 0x1.647b1ff508275p-509,
0x1.647b1ff508275p-509,
+ },
+ },
+ {
+ { 0x1.afcef51f0fb5fp+265 },
+ {
+ -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
-0x1.53e0bc0170fe8p+509,
+ 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
0x1.c3397ceebc142p+510,
+ -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
-0x1.ffe2046f999e3p+511,
+ -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
-0x1.94d2a9003ee18p+510,
+ },
+ {
+ -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244, -0x1.453e40c97ee2ap-244,
-0x1.453e40c97ee2ap-244,
+ 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246, 0x1.e9f7fd1cca941p-246,
0x1.e9f7fd1cca941p-246,
+ -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247, -0x1.afe83ffcda969p-247,
-0x1.afe83ffcda969p-247,
+ -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245, -0x1.1110a2fba3e0dp-245,
-0x1.1110a2fba3e0dp-245,
+ },
+ },
+ {
+ { -0x1.ed8d34e547314p+597 },
+ {
+ -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
-0x1.062a35a13cec0p+509,
+ -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
-0x1.e5739808c344dp+511,
+ 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
0x1.96d5c3ca79e38p+508,
+ -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
-0x1.08eb6307cef78p+509,
+ },
+ {
+ 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88, 0x1.e1f211cce49a8p+88,
0x1.e1f211cce49a8p+88,
+ 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86, 0x1.044581e6878d3p+86,
0x1.044581e6878d3p+86,
+ -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89, -0x1.3690f29d3d5d0p+89,
-0x1.3690f29d3d5d0p+89,
+ 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88, 0x1.dcef333871e2dp+88,
0x1.dcef333871e2dp+88,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c
new file mode 100644
index 000000000000..07fb5404c213
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f16.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T _Float16
+#define NAME rdiv
+
+DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T,
NAME, out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c
new file mode 100644
index 000000000000..1ebc9a4441d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f32.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T float
+#define NAME rdiv
+
+DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T,
NAME, out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c
new file mode 100644
index 000000000000..53dc9f9f4003
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrdiv-run-1-f64.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T double
+#define NAME rdiv
+
+DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, /, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T,
NAME, out, in, f, n)
+
+#include "vf_binop_run.h"
