https://gcc.gnu.org/g:1f01c51abff55301149f1057aaf0e7d7784bd6cc
commit r16-3658-g1f01c51abff55301149f1057aaf0e7d7784bd6cc
Author: Paul-Antoine Arras <par...@baylibre.com>
Date: Fri Sep 5 13:03:40 2025 +0200
RISC-V: Add pattern for vector-scalar single-width floating-point sub
This pattern enables the combine pass (or late-combine, depending on the
case)
to merge a vec_duplicate into a minus RTL instruction. The vec_duplicate is
the
subtrahend operand.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfsub.vv v1,v1,v2
After, we get only one:
vfsub.vf v1,v1,fa0
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfsub_vf_<mode>): New pattern to
combine vec_duplicate + vfsub.vv into vfsub.vf.
* config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS
modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: Adjust
scan
dumps.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfsub.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
vfsub.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c: New test.
Diff:
---
gcc/config/riscv/autovec-opt.md | 19 +++
gcc/config/riscv/vector.md | 12 +-
.../riscv/rvv/autovec/vls/floating-point-sub-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vf_binop_data.h | 146 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c | 19 +++
.../riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c | 15 +++
.../riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c | 15 +++
19 files changed, 239 insertions(+), 7 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index f51b8ba80523..f4d13ca35684 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2188,3 +2188,22 @@
}
[(set_attr "type" "vfalu")]
)
+
+;; vfsub.vf
+(define_insn_and_split "*vfsub_vf_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (minus:V_VLSF
+ (match_operand:V_VLSF 1 "register_operand")
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (MINUS, <MODE>mode),
+ riscv_vector::BINARY_OP_FRM_DYN, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfalu")]
+)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index d62f8bb2cd2e..c6c37dff9945 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6441,8 +6441,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
@@ -6453,11 +6453,11 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (non_commutative_float_binop:VF
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
- (vec_duplicate:VF
+ (non_commutative_float_binop:V_VLSF
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
+ (vec_duplicate:V_VLSF
(match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
0")))]
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
index 8ddefc69f2c4..e8a1bc69d71d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
@@ -39,5 +39,5 @@ DEF_OP_VX (sub, 128, double, -)
DEF_OP_VX (sub, 256, double, -)
DEF_OP_VX (sub, 512, double, -)
-/* { dg-final { scan-assembler-times
{vfsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times
{vfsub\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index ad3e1999d3eb..002d091c3adc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -18,6 +18,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
DEF_VF_BINOP_CASE_0 (_Float16, +, add)
+DEF_VF_BINOP_CASE_0 (_Float16, -, sub)
DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min)
DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
@@ -39,6 +40,7 @@ DEF_VF_BINOP_WIDEN_CASE_0 (_Float16, float, *, mul)
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfsub.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
/* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index dae2d04c3ede..c8b323b63e79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -18,6 +18,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
DEF_VF_BINOP_CASE_0 (float, *, mul)
DEF_VF_BINOP_CASE_0 (float, +, add)
+DEF_VF_BINOP_CASE_0 (float, -, sub)
DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min)
DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
@@ -39,6 +40,7 @@ DEF_VF_BINOP_WIDEN_CASE_0 (float, double, *, mul)
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfsub.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
/* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index cb36ef846939..0d04b9231181 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -14,6 +14,7 @@ DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
DEF_VF_BINOP_CASE_0 (double, *, mul)
DEF_VF_BINOP_CASE_0 (double, +, add)
+DEF_VF_BINOP_CASE_0 (double, -, sub)
DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min)
DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
@@ -30,6 +31,7 @@ DEF_VF_BINOP_CASE_2_WRAP (double, MAX_FUNC_1_WRAP (double),
max)
/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfsub.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
/* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index eebb69f30915..05361d8191c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -17,6 +17,7 @@
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfadd.vf} } } */
+/* { dg-final { scan-assembler-not {vfsub.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index 64ab5b191e14..085d8727daca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -17,6 +17,7 @@
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfadd.vf} } } */
+/* { dg-final { scan-assembler-not {vfsub.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index b8497170d30e..49ad3863a213 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -13,6 +13,7 @@
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfadd.vf} } } */
+/* { dg-final { scan-assembler-not {vfsub.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 12e779c8a3c9..e1d7730ec239 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -18,6 +18,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
DEF_VF_BINOP_CASE_1 (_Float16, +, add, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_CASE_1 (_Float16, -, sub, VF_BINOP_BODY_X128)
DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min,
VF_BINOP_FUNC_BODY_X128)
@@ -43,6 +44,7 @@ DEF_VF_BINOP_WIDEN_CASE_1 (_Float16, float, *, mul)
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfadd.vf} } } */
+/* { dg-final { scan-assembler {vfsub.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {vfmin.vf} } } */
/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index 49ebc2bbace3..bef9a2d41cbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -18,6 +18,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc)
DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
DEF_VF_BINOP_CASE_1 (float, +, add, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_CASE_1 (float, -, sub, VF_BINOP_BODY_X128)
DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min,
VF_BINOP_FUNC_BODY_X128)
@@ -43,6 +44,7 @@ DEF_VF_BINOP_WIDEN_CASE_1 (float, double, *, mul)
/* { dg-final { scan-assembler {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfadd.vf} } } */
+/* { dg-final { scan-assembler {vfsub.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {vfmin.vf} } } */
/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 9f898d2d2491..861da77a82bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -14,6 +14,7 @@ DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc,
VF_MULOP_ACC_BODY_X128)
DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
DEF_VF_BINOP_CASE_1 (double, +, add, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_CASE_1 (double, -, sub, VF_BINOP_BODY_X128)
DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min,
VF_BINOP_FUNC_BODY_X128)
@@ -34,6 +35,7 @@ DEF_VF_BINOP_CASE_3_WRAP (double, MAX_FUNC_1_WRAP (double),
max,
/* { dg-final { scan-assembler {vfnmsac.vf} } } */
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfadd.vf} } } */
+/* { dg-final { scan-assembler {vfsub.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {vfmin.vf} } } */
/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index eab87ef60222..19456dcb16c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -17,6 +17,7 @@
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfadd.vf} } } */
+/* { dg-final { scan-assembler-not {vfsub.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index 5cd4d57a23b4..9c3a59f28ef8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -17,6 +17,7 @@
/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfadd.vf} } } */
+/* { dg-final { scan-assembler-not {vfsub.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index 437631c6626f..14cf691ca6fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -13,6 +13,7 @@
/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfadd.vf} } } */
+/* { dg-final { scan-assembler-not {vfsub.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
index 48f7a26b9d2b..d7f8d1dcd458 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -300,6 +300,152 @@ double TEST_BINOP_DATA(double, add)[][4][N] =
},
},
};
+_Float16 TEST_BINOP_DATA(_Float16, sub)[][4][N] =
+{
+ {
+ { 0x1.0000000000000p+0f16 },
+ {
+ 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
0x1.8fc0000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
0x1.a4c0000000000p+5f16,
+ 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
0x1.6f80000000000p+4f16,
+ },
+ {
+ 0x1.7fc0000000000p+4f16, 0x1.7fc0000000000p+4f16, 0x1.7fc0000000000p+4f16,
0x1.7fc0000000000p+4f16,
+ 0x1.b480000000000p+6f16, 0x1.b480000000000p+6f16, 0x1.b480000000000p+6f16,
0x1.b480000000000p+6f16,
+ 0x1.9cc0000000000p+5f16, 0x1.9cc0000000000p+5f16, 0x1.9cc0000000000p+5f16,
0x1.9cc0000000000p+5f16,
+ 0x1.5f80000000000p+4f16, 0x1.5f80000000000p+4f16, 0x1.5f80000000000p+4f16,
0x1.5f80000000000p+4f16,
+ },
+ },
+ {
+ { 0x1.9000000000000p+6f16 },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
-0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
0x1.c300000000000p+6f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
-0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
-0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ {
+ -0x1.1d00000000000p+7f16, -0x1.1d00000000000p+7f16,
-0x1.1d00000000000p+7f16, -0x1.1d00000000000p+7f16,
+ 0x1.9800000000000p+3f16, 0x1.9800000000000p+3f16, 0x1.9800000000000p+3f16,
0x1.9800000000000p+3f16,
+ -0x1.63c0000000000p+8f16, -0x1.63c0000000000p+8f16,
-0x1.63c0000000000p+8f16, -0x1.63c0000000000p+8f16,
+ -0x1.9240000000000p+7f16, -0x1.9240000000000p+7f16,
-0x1.9240000000000p+7f16, -0x1.9240000000000p+7f16,
+ },
+ },
+ {
+ { -0x1.9000000000000p+6f16 },
+ {
+ -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
-0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+ -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
-0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+ 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
0x1.96c0000000000p+4f16,
+ -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
-0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+ },
+ {
+ 0x1.0d00000000000p+6f16, 0x1.0d00000000000p+6f16, 0x1.0d00000000000p+6f16,
0x1.0d00000000000p+6f16,
+ -0x1.1d40000000000p+7f16, -0x1.1d40000000000p+7f16,
-0x1.1d40000000000p+7f16, -0x1.1d40000000000p+7f16,
+ 0x1.f5c0000000000p+6f16, 0x1.f5c0000000000p+6f16, 0x1.f5c0000000000p+6f16,
0x1.f5c0000000000p+6f16,
+ 0x1.0b80000000000p+6f16, 0x1.0b80000000000p+6f16, 0x1.0b80000000000p+6f16,
0x1.0b80000000000p+6f16,
+ },
+ },
+};
+
+float TEST_BINOP_DATA(float, sub)[][4][N] =
+{
+ {
+ { 0x1.1c37940000000p+53f },
+ {
+ 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
0x1.8fe1540000000p+60f,
+ 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
0x1.b8b5320000000p+62f,
+ 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
0x1.a4eb340000000p+61f,
+ 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
0x1.6faeda0000000p+60f,
+ },
+ {
+ 0x1.8da8e60000000p+60f, 0x1.8da8e60000000p+60f, 0x1.8da8e60000000p+60f,
0x1.8da8e60000000p+60f,
+ 0x1.b827160000000p+62f, 0x1.b827160000000p+62f, 0x1.b827160000000p+62f,
0x1.b827160000000p+62f,
+ 0x1.a3cefc0000000p+61f, 0x1.a3cefc0000000p+61f, 0x1.a3cefc0000000p+61f,
0x1.a3cefc0000000p+61f,
+ 0x1.6d766a0000000p+60f, 0x1.6d766a0000000p+60f, 0x1.6d766a0000000p+60f,
0x1.6d766a0000000p+60f,
+ },
+ },
+ {
+ { 0x1.158e460000000p+63f },
+ {
+ -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
-0x1.53e0ba0000000p+61f,
+ 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
0x1.c3397c0000000p+62f,
+ -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
-0x1.ffe2020000000p+63f,
+ -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
-0x1.94d2a80000000p+62f,
+ },
+ {
+ -0x1.6a86740000000p+63f, -0x1.6a86740000000p+63f, -0x1.6a86740000000p+63f,
-0x1.6a86740000000p+63f,
+ -0x1.9f8c440000000p+60f, -0x1.9f8c440000000p+60f, -0x1.9f8c440000000p+60f,
-0x1.9f8c440000000p+60f,
+ -0x1.8ab8240000000p+64f, -0x1.8ab8240000000p+64f, -0x1.8ab8240000000p+64f,
-0x1.8ab8240000000p+64f,
+ -0x1.dff79a0000000p+63f, -0x1.dff79a0000000p+63f, -0x1.dff79a0000000p+63f,
-0x1.dff79a0000000p+63f,
+ },
+ },
+ {
+ { -0x1.158e460000000p+63f },
+ {
+ -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
-0x1.53e0ba0000000p+61f,
+ 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
0x1.c3397c0000000p+62f,
+ -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
-0x1.ffe2020000000p+63f,
+ -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
-0x1.94d2a80000000p+62f,
+ },
+ {
+ 0x1.812c2e0000000p+62f, 0x1.812c2e0000000p+62f, 0x1.812c2e0000000p+62f,
0x1.812c2e0000000p+62f,
+ 0x1.f72b040000000p+63f, 0x1.f72b040000000p+63f, 0x1.f72b040000000p+63f,
0x1.f72b040000000p+63f,
+ -0x1.d4a7780000000p+62f, -0x1.d4a7780000000p+62f, -0x1.d4a7780000000p+62f,
-0x1.d4a7780000000p+62f,
+ 0x1.2c93ca0000000p+61f, 0x1.2c93ca0000000p+61f, 0x1.2c93ca0000000p+61f,
0x1.2c93ca0000000p+61f,
+ },
+ },
+};
+
+double TEST_BINOP_DATA(double, sub)[][4][N] =
+{
+ {
+ { 0x1.12f1bbdb4d470p+508 },
+ {
+ 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
0x1.8fe1565f12a78p+508,
+ 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
0x1.b8b533d821ccap+510,
+ 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
0x1.a4eb35b744a54p+509,
+ 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
0x1.6faedb6395f48p+508,
+ },
+ {
+ 0x1.f3be6a0f15820p+506, 0x1.f3be6a0f15820p+506, 0x1.f3be6a0f15820p+506,
0x1.f3be6a0f15820p+506,
+ 0x1.73f8c4e14e7aep+510, 0x1.73f8c4e14e7aep+510, 0x1.73f8c4e14e7aep+510,
0x1.73f8c4e14e7aep+510,
+ 0x1.1b7257c99e01cp+509, 0x1.1b7257c99e01cp+509, 0x1.1b7257c99e01cp+509,
0x1.1b7257c99e01cp+509,
+ 0x1.72f47e2122b60p+506, 0x1.72f47e2122b60p+506, 0x1.72f47e2122b60p+506,
0x1.72f47e2122b60p+506,
+ },
+ },
+ {
+ { 0x1.57ae2ad22098cp+511 },
+ {
+ -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
-0x1.53e0bc0170fe8p+509,
+ 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
0x1.c3397ceebc142p+510,
+ -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
-0x1.ffe2046f999e3p+511,
+ -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
-0x1.94d2a9003ee18p+510,
+ },
+ {
+ -0x1.aca659d27cd86p+511, -0x1.aca659d27cd86p+511, -0x1.aca659d27cd86p+511,
-0x1.aca659d27cd86p+511,
+ -0x1.d845b16b0a3acp+509, -0x1.d845b16b0a3acp+509, -0x1.d845b16b0a3acp+509,
-0x1.d845b16b0a3acp+509,
+ -0x1.abc817a0dd1b8p+512, -0x1.abc817a0dd1b8p+512, -0x1.abc817a0dd1b8p+512,
-0x1.abc817a0dd1b8p+512,
+ -0x1.110bbfa92004cp+512, -0x1.110bbfa92004cp+512, -0x1.110bbfa92004cp+512,
-0x1.110bbfa92004cp+512,
+ },
+ },
+ {
+ { -0x1.57ae2ad22098cp+511 },
+ {
+ -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
-0x1.062a35a13cec0p+509,
+ -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
-0x1.e5739808c344dp+511,
+ 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
0x1.96d5c3ca79e38p+508,
+ -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
-0x1.08eb6307cef78p+509,
+ },
+ {
+ 0x1.16239d69d15dcp+511, 0x1.16239d69d15dcp+511, 0x1.16239d69d15dcp+511,
0x1.16239d69d15dcp+511,
+ -0x1.1b8ada6d45582p+510, -0x1.1b8ada6d45582p+510, -0x1.1b8ada6d45582p+510,
-0x1.1b8ada6d45582p+510,
+ 0x1.8a88e34b6fd53p+511, 0x1.8a88e34b6fd53p+511, 0x1.8a88e34b6fd53p+511,
0x1.8a88e34b6fd53p+511,
+ 0x1.157352102cdaep+511, 0x1.157352102cdaep+511, 0x1.157352102cdaep+511,
0x1.157352102cdaep+511,
+ },
+ },
+};
_Float16 TEST_BINOP_DATA(_Float16, rdiv)[][4][N] =
{
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c
new file mode 100644
index 000000000000..4428e43c2cb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T _Float16
+#define NAME sub
+
+DEF_VF_BINOP_CASE_0_WRAP (T, -, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME,
out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c
new file mode 100644
index 000000000000..bcfdcc2a3d00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T float
+#define NAME sub
+
+DEF_VF_BINOP_CASE_0_WRAP (T, -, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME,
out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c
new file mode 100644
index 000000000000..fee8ecfd1ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T double
+#define NAME sub
+
+DEF_VF_BINOP_CASE_0_WRAP (T, -, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME,
out, in, f, n)
+
+#include "vf_binop_run.h"
