https://gcc.gnu.org/g:f8a1436462abb212e8de0d5bc5ccc0d9f9e0b974
commit r16-3655-gf8a1436462abb212e8de0d5bc5ccc0d9f9e0b974
Author: Paul-Antoine Arras <par...@baylibre.com>
Date: Mon Sep 1 15:54:26 2025 +0200
RISC-V: Add patterns for vector-scalar IEEE floating-point max
These patterns enable the combine pass (or late-combine, depending on the
case)
to merge a vec_duplicate into an unspec_vfmax RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfmax.vv v1,v2,v1
After, we get only one:
vfmax.vf v1,v1,fa0
In some cases, it also shaves off one vsetvli.
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfmin_vf_ieee_<mode>): Rename
into...
(*v<ieee_fmaxmin_op>_vf_<mode>): New pattern to combine
vec_duplicate +
vf{max,min}.vv (unspec) into vf{max,min}.vf.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c: Add vfmax.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c: Add vfmax. Also add
missing -fno-fast-math.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c: Likewise.
Diff:
---
gcc/config/riscv/autovec-opt.md | 14 ++++++++------
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c | 2 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c | 2 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c | 2 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c | 1 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c | 6 +++++-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c | 2 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c | 2 ++
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c | 3 ++-
13 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 328ee0e096fe..d2a89a5d63b4 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2107,38 +2107,40 @@
[(set_attr "type" "vfminmax")]
)
-(define_insn_and_split "*vfmin_vf_ieee_<mode>"
+(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(unspec:V_VLSF [
(vec_duplicate:V_VLSF
(match_operand:<VEL> 2 "register_operand"))
(match_operand:V_VLSF 1 "register_operand")
- ] UNSPEC_VFMIN))]
+ ] UNSPEC_VFMAXMIN))]
"TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_insn (code_for_pred_scalar (UNSPEC_VFMIN,
<MODE>mode),
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<IEEE_FMAXMIN_OP>,
+ <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
[(set_attr "type" "vfminmax")]
)
-(define_insn_and_split "*vfmin_vf_ieee_<mode>"
+(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(unspec:V_VLSF [
(match_operand:V_VLSF 1 "register_operand")
(vec_duplicate:V_VLSF
(match_operand:<VEL> 2 "register_operand"))
- ] UNSPEC_VFMIN))]
+ ] UNSPEC_VFMAXMIN))]
"TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_insn (code_for_pred_scalar (UNSPEC_VFMIN,
<MODE>mode),
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<IEEE_FMAXMIN_OP>,
+ <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
index 1a20ee78536b..ba8eec0bb7ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
@@ -4,5 +4,7 @@
#include "vf_binop.h"
DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fminf16, min)
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fmaxf16, max)
/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
index 1e0f7f5cb154..b5a1991ab899 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
@@ -4,5 +4,7 @@
#include "vf_binop.h"
DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fminf, min)
+DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fmaxf, max)
/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
index 61db2df4521a..a6fc781d87a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
@@ -4,5 +4,7 @@
#include "vf_binop.h"
DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmin, min)
+DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmax, max)
/* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
index 392580abddcc..afd64e78072a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
@@ -4,3 +4,4 @@
#include "vf-5-f16.c"
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
index 9dbd226c0428..edcecffdf061 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
@@ -4,3 +4,4 @@
#include "vf-5-f32.c"
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
index 44a17cd1ff6a..fafaa254cd9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
@@ -4,3 +4,4 @@
#include "vf-5-f64.c"
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
index 0883c882201a..362fdfa69c0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
@@ -3,6 +3,10 @@
#include "vf_binop.h"
-DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min,
VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fmaxf16, max,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
index 85282404ad27..2944a35451d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
@@ -4,5 +4,7 @@
#include "vf_binop.h"
DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fminf, min, VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fmaxf, max, VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
index 474b33900ce8..f785f8558202 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
@@ -4,5 +4,7 @@
#include "vf_binop.h"
DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmin, min, VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmax, max, VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
index bd68b3cdf220..5c91c88a920a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math
--param=fpr2vr-cost=4" } */
#include "vf-7-f16.c"
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
index 000402c1520b..13237f128979 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math
--param=fpr2vr-cost=4" } */
#include "vf-7-f32.c"
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
index 89dec81fba4c..109913c4290b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math
--param=fpr2vr-cost=4" } */
#include "vf-7-f64.c"
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
