https://gcc.gnu.org/g:fdc9da32dc65872c4a7f0ba9b45448181555c61a
commit fdc9da32dc65872c4a7f0ba9b45448181555c61a
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon Sep 8 15:46:25 2025 -0400
PR target/117251: Improve vector eqv to vector nand fusion
See the following post for a complete explanation of what the patches
for PR target/117251:
* https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html
This is patch #39 of 45 to generate the 'XXEVAL' instruction on power10
and power11 instead of using the Altivec 'VEQV' instruction feeding
into 'VNAND'. The 'XXEVAL' instruction can use all 64 vector
registers, instead of the 32 registers that traditional Altivec vector
instructions use. By allowing all of the vector registers to be used,
it reduces the amount of spilling that a large benchmark generated.
Currently the following code:
vector int a, b, c, d;
a = ~ ((~ (c ^ d)) & b);
Generates:
veqv t,c,d
vnand a,t,b
Now in addition with this patch, if the arguments or result is
allocated to a traditional FPR register, the GCC compiler will now
generate the following code instead of adding vector move instructions:
xxeval a,b,c,246
Since fusion using 2 Altivec instructions is slightly faster than using
the 'XXEVAL' instruction we prefer to generate the Altivec instructions
if we can. In addition, because 'XXEVAL' is a prefixed instruction, it
possibly might generate an extra NOP instruction to align the 'XXEVAL'
instruction.
I have tested these patches on both big endian and little endian
PowerPC servers, with no regressions. Can I check these patchs into
the trunk?
2025-09-08 Michael Meissner <meiss...@linux.ibm.com>
gcc/
PR target/117251
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/genfusion.pl (gen_logical_addsubf): Add support
to generate vector eqv => nand fusion if XXEVAL is supported.
Diff:
---
gcc/config/rs6000/fusion.md | 15 +++++++++------
gcc/config/rs6000/genfusion.pl | 1 +
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 96d8951049c9..c1be0e5ff8f1 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2372,20 +2372,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnand
(define_insn "*fuse_veqv_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,246
veqv %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,xxeval,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnand
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 77d3e999eb93..4c70237d2d27 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -253,6 +253,7 @@ sub gen_logical_addsubf
"vnand_vor" => 239,
"vnand_vnand" => 241,
"vorc_vnand" => 244,
+ "veqv_vnand" => 246,
);
KIND: foreach $kind ('scalar','vector') {
