https://gcc.gnu.org/g:881dc2df1de2d1996344bf41e70253a199ec554b
commit 881dc2df1de2d1996344bf41e70253a199ec554b
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Sep 11 20:57:05 2025 -0400
Add -mbfloat16 converts.
2025-09-11 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000.md (FP16_CONVERT): Rename from HF_CONVERT.
(extend<FP16:mode><FP16_CONVERT:mode>2): Extend to allow both 16-bit
floating point types.
(trunc<FP16_CONVERT:mode><FP16:mode>2): Likewise.
(float<GPR:mode><FP16:mode>2): Likewise.
(floatuns<GPR:mode><FP16:mode>2): Likewise.
(fix_trunc<FP16:mode><GPR:mode>2): Likewise.
(fixuns_trunc<FP16:mode><GPR:mode>2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.md | 163 +++++++++++++++++++++++---------------------
1 file changed, 86 insertions(+), 77 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4ab420d1637f..4fa59ab54824 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -865,7 +865,7 @@
;; Mode iterator for floating point modes other than SF/DFmode that we
;; convert to/from _Float16 (HFmode) via DFmode.
-(define_mode_iterator HF_CONVERT [TF KF IF SD DD TD])
+(define_mode_iterator FP16_CONVERT [TF KF IF SD DD TD])
(include "darwin.md")
@@ -5878,82 +5878,6 @@
"xscvdphp %x0,%1"
[(set_attr "type" "fpsimple")])
-;; Use DFmode to convert to/from HFmode for floating point types other
-;; than SF/DFmode.
-(define_expand "extendhf<mode>2"
- [(set (match_operand:HF_CONVERT 0 "vsx_register_operand" "=wa")
- (float_extend:HF_CONVERT
- (match_operand:HF 1 "vsx_register_operand" "wa")))]
- "TARGET_IEEE16"
-{
- rtx df_tmp = gen_reg_rtx (DFmode);
- convert_move (df_tmp, operands[1], 0);
- convert_move (operands[0], df_tmp, 0);
- DONE;
-})
-
-(define_expand "trunc<mode>hf2"
- [(set (match_operand:HF 0 "vsx_register_operand" "=wa")
- (float_truncate:HF
- (match_operand:HF_CONVERT 1 "vsx_register_operand" "wa")))]
- "TARGET_IEEE16"
-{
- rtx df_tmp = gen_reg_rtx (DFmode);
- convert_move (df_tmp, operands[1], 0);
- convert_move (operands[0], df_tmp, 0);
- DONE;
-})
-
-;; Convert integers to 16-bit floating point modes.
-(define_expand "float<GPR:mode>hf2"
- [(set (match_operand:HF 0 "vsx_register_operand")
- (float:HF
- (match_operand:GPR 1 "nonimmediate_operand")))]
- ""
-{
- rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_float<mode>df2 (df_tmp, operands[1]));
- emit_insn (gen_truncdfhf2 (operands[0], df_tmp));
- DONE;
-})
-
-(define_expand "floatuns<GPR:mode>hf2"
- [(set (match_operand:HF 0 "vsx_register_operand")
- (unsigned_float:HF
- (match_operand:GPR 1 "nonimmediate_operand")))]
- ""
-{
- rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_floatuns<mode>df2 (df_tmp, operands[1]));
- emit_insn (gen_truncdfhf2 (operands[0], df_tmp));
- DONE;
-})
-
-;; Convert 16-bit floating point modes to integers
-(define_expand "fix_trunchf<mode>2"
- [(set (match_operand:GPR 0 "vsx_register_operand")
- (fix:GPR
- (match_operand:HF 1 "vsx_register_operand")))]
- ""
-{
- rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_extendhfdf2 (df_tmp, operands[1]));
- emit_insn (gen_fix_truncdf<mode>2 (operands[0], df_tmp));
- DONE;
-})
-
-(define_expand "fixuns_trunchf<mode>2"
- [(set (match_operand:GPR 0 "vsx_register_operand")
- (unsigned_fix:GPR
- (match_operand:HF 1 "vsx_register_operand")))]
- ""
-{
- rtx df_tmp = gen_reg_rtx (DFmode);
- emit_insn (gen_extendhfdf2 (df_tmp, operands[1]));
- emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp));
- DONE;
-})
-
;; Convert BFmode to SFmode/DFmode.
;; 3 instructions are generated:
;; VSPLTH -- duplicate BFmode into all elements
@@ -6025,6 +5949,91 @@
}
[(set_attr "type" "fpsimple")])
+;; Use DFmode to convert to/from 16-bit floating point types for
+;; scalar floating point types other than SF/DFmode.
+(define_expand "extend<FP16:mode><FP16_CONVERT:mode>2"
+ [(set (match_operand:FP16_CONVERT 0 "vsx_register_operand")
+ (float_extend:FP16_CONVERT
+ (match_operand:FP16 1 "vsx_register_operand")))]
+ ""
+{
+ rtx df_tmp = gen_reg_rtx (DFmode);
+ emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+
+ /* convert_move handles things like conversion to Decimal types that
+ we don't have extenddfdd2 insns, so a call is made to do the
+ conversion. */
+ convert_move (operands[0], df_tmp, 0);
+ DONE;
+})
+
+(define_expand "trunc<FP16_CONVERT:mode><FP16:mode>2"
+ [(set (match_operand:FP16 0 "vsx_register_operand")
+ (float_truncate:FP16
+ (match_operand:FP16_CONVERT 1 "vsx_register_operand")))]
+ ""
+{
+ rtx df_tmp = gen_reg_rtx (DFmode);
+
+ /* convert_move handles things like conversion from Decimal types
+ that we don't have truncdddf2 insns, so a call is made for
+ the conversion. */
+ convert_move (df_tmp, operands[1], 0);
+
+ emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+ DONE;
+})
+
+;; Convert integers to 16-bit floating point modes.
+(define_expand "float<GPR:mode><FP16:mode>2"
+ [(set (match_operand:FP16 0 "vsx_register_operand")
+ (float:FP16
+ (match_operand:GPR 1 "nonimmediate_operand")))]
+ ""
+{
+ rtx df_tmp = gen_reg_rtx (DFmode);
+ emit_insn (gen_float<GPR:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+ DONE;
+})
+
+(define_expand "floatuns<GPR:mode><FP16:mode>2"
+ [(set (match_operand:FP16 0 "vsx_register_operand")
+ (unsigned_float:FP16
+ (match_operand:GPR 1 "nonimmediate_operand")))]
+ ""
+{
+ rtx df_tmp = gen_reg_rtx (DFmode);
+ emit_insn (gen_floatuns<GPR:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_truncdf<FP16:mode>2 (operands[0], df_tmp));
+ DONE;
+})
+
+;; Convert 16-bit floating point modes to integers
+(define_expand "fix_trunc<FP16:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "vsx_register_operand")
+ (fix:GPR
+ (match_operand:FP16 1 "vsx_register_operand")))]
+ ""
+{
+ rtx df_tmp = gen_reg_rtx (DFmode);
+ emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_fix_truncdf<GPR:mode>2 (operands[0], df_tmp));
+ DONE;
+})
+
+(define_expand "fixuns_trunc<FP16:mode><GPR:mode>2"
+ [(set (match_operand:GPR 0 "vsx_register_operand")
+ (unsigned_fix:GPR
+ (match_operand:FP16 1 "vsx_register_operand")))]
+ ""
+{
+ rtx df_tmp = gen_reg_rtx (DFmode);
+ emit_insn (gen_extend<FP16:mode>df2 (df_tmp, operands[1]));
+ emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp));
+ DONE;
+})
+
;; Conversions to and from floating-point.
