https://gcc.gnu.org/g:e1c9c9d78583f31a92cfc23a6ec4592b469d2320
commit e1c9c9d78583f31a92cfc23a6ec4592b469d2320 Author: Michael Meissner <[email protected]> Date: Mon Nov 3 16:02:59 2025 -0500 Add V8HFmode, V8BFmode, HFmode, BFmode. 2025-11-03 Michael Meissner <[email protected]> gcc/ * config/rs6000/altivec.md (VM): Add V8HFmode and V8BFmode as general vector modes. Add HFmode, BFmode modes to be added in the future. (VM2): Likewise. (VI_char): Likewise. (VI_scalar): Likewise. (VI_unit): Likewise. (VP_small): Likewise. (VP_small_lc): Likewise. (VU_char): Likewise. * config/rs6000/rs6000-modes.def (HFmode): Likewise. (BFmode): Likewise. (V8BFmode): Likewise. (V8HFmode): Likewise. * config/rs6000/rs6000-p8swap.cc (rs6000_gen_stvx): Likewise. (replace_swapped_load_constant): Likewise. * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (xxspltib_constant_p): Likewise. (output_vec_const_move): Likewise. (rs6000_expand_vector_init): Likewise. (rs6000_const_vec): Likewise. (rs6000_emit_move): Likewise. * config/rs6000/rs6000.h (ALTIVEC_VECTOR_MODE): Likewise. * config/rs6000/rs6000.md (FMOVE128_GPR): Likewise. (wd): Likewise. (du_or_d): Likewise. (BOOL_128): Likewise. (BOOL_REGS_OUTPUT): Likewise. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. (RELOAD): Likewise. * config/rs6000/vector.md (VEC_L): Likewise. (VEC_M): Likewise. (VEC_E): Likewise. (VEC_base): Likewise. (VEC_base_l): Likewise. * config/rs6000/vsx.md (VECTOR_16BIT): Likewise. (VSX_L): Likewise. (VSX_M): Likewise. (VSX_XXBR): Likewise. (VSm): Likewise. (VSr): Likewise. (VSisa): Likewise. (??r): Likewise. (nW): Likewise. (VSv): Likewise. (VM3): Likewise. (VM3_char): Likewise. (vsx_le_perm_load_<mode>): Likewise. (vsx_le_perm_store_<mode>): Likewise. (V8HImode/V8HFmode/V8BFmode splitter): Likewise. (vsx_ld_elemrev_<mode>): Likewise. (vsx_ld_elemrev_<mode>_internal): Likewise. (sx_st_elemrev_<mode>): Likewise. (sx_st_elemrev_<mode>): Likewise. (vsx_st_elemrev_<mode>_interna): Likewise. (xxswapd_<mode>): Likewise. (sx_lxvd2x8_le_<MODE>): Likewise. (vsx_stxvd2x8_le_<MODE>): Likewise. (vsx_extract_<mode>_di_p9): Likewise. (*vsx_extract_<mode>_store_p9): Likewise. (vsx_extract_<mode>_p8): Likewise. Diff: --- gcc/config/rs6000/altivec.md | 34 +++++++-- gcc/config/rs6000/rs6000-modes.def | 9 +++ gcc/config/rs6000/rs6000-p8swap.cc | 14 ++-- gcc/config/rs6000/rs6000.cc | 52 ++++++++++++- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 20 ++++- gcc/config/rs6000/vector.md | 37 ++++++++- gcc/config/rs6000/vsx.md | 151 ++++++++++++++++++++++--------------- 8 files changed, 237 insertions(+), 82 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index fa3368079ada..d821960cb5f5 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -191,6 +191,8 @@ ;; otherwise handled by altivec (v2df, v2di, ti) (define_mode_iterator VM [V4SI V8HI + V8BF + V8HF V16QI V4SF V2DF @@ -203,6 +205,8 @@ ;; Like VM, except don't do TImode (define_mode_iterator VM2 [V4SI V8HI + V8BF + V8HF V16QI V4SF V2DF @@ -222,18 +226,38 @@ V1TI TI]) -(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")]) -(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")]) +(define_mode_attr VI_char [(V2DI "d") + (V4SI "w") + (V8HI "h") + (V8BF "h") + (V8HF "h") + (V16QI "b")]) +(define_mode_attr VI_scalar [(V2DI "DI") + (V4SI "SI") + (V8HI "HI") + (V8BF "BF") + (V8HF "HF") + (V16QI "QI")]) (define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)") (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)") + (V8BF "VECTOR_UNIT_ALTIVEC_P (V8BFmode)") + (V8HF "VECTOR_UNIT_ALTIVEC_P (V8HFmode)") (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)") (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")]) ;; Vector pack/unpack (define_mode_iterator VP [V2DI V4SI V8HI]) -(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")]) -(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")]) -(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")]) +(define_mode_attr VP_small [(V2DI "V4SI") + (V4SI "V8HI") + (V8HI "V16QI")]) +(define_mode_attr VP_small_lc [(V2DI "v4si") + (V4SI "v8hi") + (V8HI "v16qi")]) +(define_mode_attr VU_char [(V2DI "w") + (V4SI "h") + (V8HI "b") + (V8BF "b") + (V8HF "b")]) ;; Vector negate (define_mode_iterator VNEG [V4SI V2DI]) diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index f89e4ef403c1..916899e6b47e 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -45,6 +45,13 @@ FLOAT_MODE (TF, 16, ieee_quad_format); /* IBM 128-bit floating point. */ FLOAT_MODE (IF, 16, ibm_extended_format); +/* Explicit IEEE 16-bit floating point. */ +FLOAT_MODE (HF, 2, ieee_half_format); + +/* Explicit bfloat16 floating point. */ +FLOAT_MODE (BF, 2, arm_bfloat_half_format); +ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format); + /* Add any extra modes needed to represent the condition code. For the RS/6000, we need separate modes when unsigned (logical) comparisons @@ -70,6 +77,8 @@ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ /* Half VMX/VSX vector (for internal use) */ VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ VECTOR_MODE (INT, SI, 2); /* V2SI */ +VECTOR_MODE (FLOAT, BF, 4); /* V4BF */ +VECTOR_MODE (FLOAT, HF, 4); /* V4HF */ /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register diff --git a/gcc/config/rs6000/rs6000-p8swap.cc b/gcc/config/rs6000/rs6000-p8swap.cc index e92f01031270..7ba50f11a7bf 100644 --- a/gcc/config/rs6000/rs6000-p8swap.cc +++ b/gcc/config/rs6000/rs6000-p8swap.cc @@ -1598,10 +1598,10 @@ rs6000_gen_stvx (enum machine_mode mode, rtx dest_exp, rtx src_exp) stvx = gen_altivec_stvx_v16qi (src_exp, dest_exp); else if (mode == V8HImode) stvx = gen_altivec_stvx_v8hi (src_exp, dest_exp); -#ifdef HAVE_V8HFmode else if (mode == V8HFmode) stvx = gen_altivec_stvx_v8hf (src_exp, dest_exp); -#endif + else if (mode == V8BFmode) + stvx = gen_altivec_stvx_v8bf (src_exp, dest_exp); else if (mode == V4SImode) stvx = gen_altivec_stvx_v4si (src_exp, dest_exp); else if (mode == V4SFmode) @@ -1722,10 +1722,10 @@ rs6000_gen_lvx (enum machine_mode mode, rtx dest_exp, rtx src_exp) lvx = gen_altivec_lvx_v16qi (dest_exp, src_exp); else if (mode == V8HImode) lvx = gen_altivec_lvx_v8hi (dest_exp, src_exp); -#ifdef HAVE_V8HFmode else if (mode == V8HFmode) lvx = gen_altivec_lvx_v8hf (dest_exp, src_exp); -#endif + else if (mode == V8BFmode) + lvx = gen_altivec_lvx_v8bf (dest_exp, src_exp); else if (mode == V4SImode) lvx = gen_altivec_lvx_v4si (dest_exp, src_exp); else if (mode == V4SFmode) @@ -1930,11 +1930,7 @@ replace_swapped_load_constant (swap_web_entry *insn_entry, rtx swap_insn) rtx new_const_vector = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)); new_mem = force_const_mem (mode, new_const_vector); } - else if ((mode == V8HImode) -#ifdef HAVE_V8HFmode - || (mode == V8HFmode) -#endif - ) + else if (mode == V8HImode || mode == V8HFmode || mode == V8BFmode) { rtx vals = gen_rtx_PARALLEL (mode, rtvec_alloc (8)); int i; diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 44bcf9664121..6d57d3fd1784 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -2272,6 +2272,8 @@ rs6000_debug_reg_global (void) V8SImode, V4DImode, V2TImode, + V8BFmode, + V8HFmode, V4SFmode, V2DFmode, V8SFmode, @@ -2896,18 +2898,24 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC; rs6000_vector_align[V4SImode] = align32; rs6000_vector_align[V8HImode] = align32; + rs6000_vector_align[V8HFmode] = align32; + rs6000_vector_align[V8BFmode] = align32; rs6000_vector_align[V16QImode] = align32; if (TARGET_VSX) { rs6000_vector_mem[V4SImode] = VECTOR_VSX; rs6000_vector_mem[V8HImode] = VECTOR_VSX; + rs6000_vector_mem[V8HFmode] = VECTOR_VSX; + rs6000_vector_mem[V8BFmode] = VECTOR_VSX; rs6000_vector_mem[V16QImode] = VECTOR_VSX; } else { rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC; rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC; + rs6000_vector_mem[V8HFmode] = VECTOR_ALTIVEC; + rs6000_vector_mem[V8BFmode] = VECTOR_ALTIVEC; rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC; } } @@ -3008,6 +3016,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load; reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store; reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load; + reg_addr[V8BFmode].reload_store = CODE_FOR_reload_v8bf_di_store; + reg_addr[V8BFmode].reload_load = CODE_FOR_reload_v8bf_di_load; + reg_addr[V8HFmode].reload_store = CODE_FOR_reload_v8hf_di_store; + reg_addr[V8HFmode].reload_load = CODE_FOR_reload_v8hf_di_load; reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store; reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load; reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store; @@ -3059,6 +3071,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di; reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf; reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si; + reg_addr[V8BFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8bf; + reg_addr[V8HFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hf; reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi; reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi; reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf; @@ -3069,6 +3083,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di; reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf; reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si; + reg_addr[V8BFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8bf; + reg_addr[V8HFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hf; reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi; reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi; reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf; @@ -3106,6 +3122,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load; reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store; reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load; + reg_addr[V8BFmode].reload_store = CODE_FOR_reload_v8bf_si_store; + reg_addr[V8BFmode].reload_load = CODE_FOR_reload_v8bf_si_load; + reg_addr[V8HFmode].reload_store = CODE_FOR_reload_v8hf_si_store; + reg_addr[V8HFmode].reload_load = CODE_FOR_reload_v8hf_si_load; reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store; reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load; reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; @@ -6559,6 +6579,12 @@ xxspltib_constant_p (rtx op, /* Handle (vec_duplicate <constant>). */ if (GET_CODE (op) == VEC_DUPLICATE) { + element = XEXP (op, 0); + + /* For V8BFmode & V8HFmode, the only valid to use xxspltib is 0.0. */ + if (mode == V8BFmode || mode == V8HFmode) + return element == CONST0_RTX (GET_MODE_INNER (mode)); + if (mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode) return false; @@ -6575,6 +6601,20 @@ xxspltib_constant_p (rtx op, /* Handle (const_vector [...]). */ else if (GET_CODE (op) == CONST_VECTOR) { + /* For V8BFmode & V8HFmode, the only valid to use xxspltib is 0.0. */ + if (mode == V8BFmode || mode == V8HFmode) + { + if (op == CONST0_RTX (mode)) + return true; + + rtx zero = CONST0_RTX (GET_MODE_INNER (mode)); + for (i = 0; i < nunits; i++) + if (CONST_VECTOR_ELT (op, i) != zero) + return false; + + return true; + } + if (mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode) return false; @@ -6791,6 +6831,8 @@ output_vec_const_move (rtx *operands) return "vspltisw %0,%1"; case E_V8HImode: + case E_V8HFmode: + case E_V8BFmode: return "vspltish %0,%1"; case E_V16QImode: @@ -7082,7 +7124,9 @@ rs6000_expand_vector_init (rtx target, rtx vals) return; } - if (TARGET_DIRECT_MOVE && (mode == V16QImode || mode == V8HImode)) + if (TARGET_DIRECT_MOVE + && (mode == V16QImode || mode == V8HImode || mode == V8HFmode + || mode == V8BFmode)) { rtx op[16]; /* Force the values into word_mode registers. */ @@ -8657,6 +8701,8 @@ reg_offset_addressing_ok_p (machine_mode mode) { case E_V16QImode: case E_V8HImode: + case E_V8HFmode: + case E_V8BFmode: case E_V4SFmode: case E_V4SImode: case E_V2DFmode: @@ -10762,6 +10808,8 @@ rs6000_const_vec (machine_mode mode) subparts = 4; break; case E_V8HImode: + case E_V8HFmode: + case E_V8BFmode: subparts = 8; break; case E_V16QImode: @@ -11217,6 +11265,8 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode) case E_V16QImode: case E_V8HImode: + case E_V8HFmode: + case E_V8BFmode: case E_V4SFmode: case E_V4SImode: case E_V2DFmode: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 643aa2449318..c31fd1a7e0f5 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -991,6 +991,8 @@ enum data_align { align_abi, align_opt, align_both }; #define ALTIVEC_VECTOR_MODE(MODE) \ ((MODE) == V16QImode \ || (MODE) == V8HImode \ + || (MODE) == V8HFmode \ + || (MODE) == V8BFmode \ || (MODE) == V4SFmode \ || (MODE) == V4SImode \ || VECTOR_ALIGNMENT_P (MODE)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index edb624fcc9e7..f6cb7d7f4819 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -552,6 +552,8 @@ (define_mode_iterator FMOVE128_GPR [TI V16QI V8HI + V8BF + V8HF V4SI V4SF V2DI @@ -716,6 +718,8 @@ (DI "d") (V16QI "b") (V8HI "h") + (V8BF "h") + (V8HF "h") (V4SI "w") (V2DI "d") (V1TI "q") @@ -728,6 +732,8 @@ (DI "d") (V16QI "du") (V8HI "du") + (V8BF "du") + (V8HF "du") (V4SI "du") (V2DI "d")]) @@ -777,6 +783,8 @@ PTI (V16QI "TARGET_ALTIVEC") (V8HI "TARGET_ALTIVEC") + (V8BF "TARGET_ALTIVEC") + (V8HF "TARGET_ALTIVEC") (V4SI "TARGET_ALTIVEC") (V4SF "TARGET_ALTIVEC") (V2DI "TARGET_ALTIVEC") @@ -794,6 +802,8 @@ (PTI "&r,r,r") (V16QI "wa,v,&?r,?r,?r") (V8HI "wa,v,&?r,?r,?r") + (V8BF "wa,v,&?r,?r,?r") + (V8HF "wa,v,&?r,?r,?r") (V4SI "wa,v,&?r,?r,?r") (V4SF "wa,v,&?r,?r,?r") (V2DI "wa,v,&?r,?r,?r") @@ -805,6 +815,8 @@ (PTI "r,0,r") (V16QI "wa,v,r,0,r") (V8HI "wa,v,r,0,r") + (V8BF "wa,v,r,0,r") + (V8HF "wa,v,r,0,r") (V4SI "wa,v,r,0,r") (V4SF "wa,v,r,0,r") (V2DI "wa,v,r,0,r") @@ -816,6 +828,8 @@ (PTI "r,r,0") (V16QI "wa,v,r,r,0") (V8HI "wa,v,r,r,0") + (V8BF "wa,v,r,r,0") + (V8HF "wa,v,r,r,0") (V4SI "wa,v,r,r,0") (V4SF "wa,v,r,r,0") (V2DI "wa,v,r,r,0") @@ -829,6 +843,8 @@ (PTI "r,0,0") (V16QI "wa,v,r,0,0") (V8HI "wa,v,r,0,0") + (V8BF "wa,v,r,0,0") + (V8HF "wa,v,r,0,0") (V4SI "wa,v,r,0,0") (V4SF "wa,v,r,0,0") (V2DI "wa,v,r,0,0") @@ -837,8 +853,8 @@ ;; Reload iterator for creating the function to allocate a base register to ;; supplement addressing modes. -(define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI - SF SD SI DF DD DI TI PTI KF IF TF +(define_mode_iterator RELOAD [V16QI V8HI V8BF V8HF V4SI V2DI V4SF V2DF V1TI + SF SD SI DF DD DI TI PTI KF IF TF HF BF OO XO]) ;; Iterate over smin, smax diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index f5797387ca79..0b9727cca35c 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -50,11 +50,31 @@ (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF]) ;; Vector logical modes -(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI KF TF]) +(define_mode_iterator VEC_L [V16QI + V8HI + V8BF + V8HF + V4SI + V2DI + V4SF + V2DF + V1TI + TI + KF + TF]) ;; Vector modes for moves. Don't do TImode or TFmode here, since their ;; moves are handled elsewhere. -(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI KF]) +(define_mode_iterator VEC_M [V16QI + V8HI + V4SI + V2DI + V8BF + V8HF + V4SF + V2DF + V1TI + KF]) ;; Vector modes for types that don't need a realignment under VSX (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI KF TF]) @@ -63,7 +83,14 @@ (define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF V1TI]) ;; Vector init/extract modes -(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF]) +(define_mode_iterator VEC_E [V16QI + V8HI + V4SI + V2DI + V8BF + V8HF + V4SF + V2DF]) ;; Vector modes for 64-bit base types (define_mode_iterator VEC_64 [V2DI V2DF]) @@ -76,6 +103,8 @@ (V8HI "HI") (V4SI "SI") (V2DI "DI") + (V8BF "BF") + (V8HF "HF") (V4SF "SF") (V2DF "DF") (V1TI "TI") @@ -86,6 +115,8 @@ (V8HI "hi") (V4SI "si") (V2DI "di") + (V8BF "bf") + (V8HF "hf") (V4SF "sf") (V2DF "df") (V1TI "ti") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index dd3573b80868..3198802dabb9 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -46,9 +46,14 @@ ;; Iterator for vector floating point types supported by VSX (define_mode_iterator VSX_F [V4SF V2DF]) +;; Iterator for 8 element vectors +(define_mode_iterator VECTOR_16BIT [V8HI V8BF V8HF]) + ;; Iterator for logical types supported by VSX (define_mode_iterator VSX_L [V16QI V8HI + V8BF + V8HF V4SI V2DI V4SF @@ -61,6 +66,8 @@ ;; Iterator for memory moves. (define_mode_iterator VSX_M [V16QI V8HI + V8BF + V8HF V4SI V2DI V4SF @@ -71,6 +78,8 @@ TI]) (define_mode_attr VSX_XXBR [(V8HI "h") + (V8BF "h") + (V8HF "h") (V4SI "w") (V4SF "w") (V2DF "d") @@ -80,6 +89,8 @@ ;; Map into the appropriate load/store name based on the type (define_mode_attr VSm [(V16QI "vw4") (V8HI "vw4") + (V8BF "vw4") + (V8HF "vw4") (V4SI "vw4") (V4SF "vw4") (V2DF "vd2") @@ -93,6 +104,8 @@ ;; Map the register class used (define_mode_attr VSr [(V16QI "v") (V8HI "v") + (V8BF "v") + (V8HF "v") (V4SI "v") (V4SF "wa") (V2DI "wa") @@ -108,6 +121,8 @@ ;; What value we need in the "isa" field, to make the IEEE QP float work. (define_mode_attr VSisa [(V16QI "*") (V8HI "*") + (V8BF "p10") + (V8HF "p9v") (V4SI "*") (V4SF "*") (V2DI "*") @@ -124,6 +139,8 @@ ;; integer modes. (define_mode_attr ??r [(V16QI "??r") (V8HI "??r") + (V8BF "??r") + (V8HF "??r") (V4SI "??r") (V4SF "??r") (V2DI "??r") @@ -136,6 +153,8 @@ ;; A mode attribute used for 128-bit constant values. (define_mode_attr nW [(V16QI "W") (V8HI "W") + (V8BF "W") + (V8HF "W") (V4SI "W") (V4SF "W") (V2DI "W") @@ -163,6 +182,8 @@ ;; operation (define_mode_attr VSv [(V16QI "v") (V8HI "v") + (V8BF "v") + (V8HF "v") (V4SI "v") (V4SF "v") (V2DI "v") @@ -396,6 +417,8 @@ ;; Like VM2 in altivec.md, just do char, short, int, long, float and double (define_mode_iterator VM3 [V4SI V8HI + V8BF + V8HF V16QI V4SF V2DF @@ -407,6 +430,8 @@ (define_mode_attr VM3_char [(V2DI "d") (V4SI "w") (V8HI "h") + (V8BF "h") + (V8HF "h") (V16QI "b") (V2DF "d") (V4SF "w")]) @@ -541,21 +566,21 @@ [(set_attr "type" "vecload") (set_attr "length" "8")]) -(define_insn_and_split "*vsx_le_perm_load_v8hi" - [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (match_operand:V8HI 1 "indexed_or_indirect_operand" "Z"))] +(define_insn_and_split "*vsx_le_perm_load_<mode>" + [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa") + (match_operand:VECTOR_16BIT 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "&& 1" [(set (match_dup 2) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 1) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)]))) (set (match_dup 0) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 2) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) @@ -802,27 +827,27 @@ (const_int 0) (const_int 1)])))] "") -(define_insn "*vsx_le_perm_store_v8hi" - [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "=Z") - (match_operand:V8HI 1 "vsx_register_operand" "wa"))] +(define_insn "*vsx_le_perm_store_<mode>" + [(set (match_operand:VECTOR_16BIT 0 "indexed_or_indirect_operand" "=Z") + (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) (define_split - [(set (match_operand:V8HI 0 "indexed_or_indirect_operand") - (match_operand:V8HI 1 "vsx_register_operand"))] + [(set (match_operand:VECTOR_16BIT 0 "indexed_or_indirect_operand") + (match_operand:VECTOR_16BIT 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 1) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)]))) (set (match_dup 0) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 2) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) @@ -861,25 +886,25 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V8HI 0 "indexed_or_indirect_operand") - (match_operand:V8HI 1 "vsx_register_operand"))] + [(set (match_operand:VECTOR_16BIT 0 "indexed_or_indirect_operand") + (match_operand:VECTOR_16BIT 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 1) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)]))) (set (match_dup 0) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 1) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)]))) (set (match_dup 1) - (vec_select:V8HI + (vec_select:VECTOR_16BIT (match_dup 1) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) @@ -1434,15 +1459,15 @@ "lxvw4x %x0,%y1" [(set_attr "type" "vecload")]) -(define_expand "vsx_ld_elemrev_v8hi" - [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (vec_select:V8HI - (match_operand:V8HI 1 "memory_operand" "Z") +(define_expand "vsx_ld_elemrev_<mode>" + [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "memory_operand" "Z") (parallel [(const_int 7) (const_int 6) (const_int 5) (const_int 4) (const_int 3) (const_int 2) (const_int 1) (const_int 0)])))] - "VECTOR_MEM_VSX_P (V8HImode) && !BYTES_BIG_ENDIAN" + "VECTOR_MEM_VSX_P (<MODE>mode) && !BYTES_BIG_ENDIAN" { if (!TARGET_P9_VECTOR) { @@ -1452,9 +1477,9 @@ unsigned int reorder[16] = {13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2}; int i; - subreg = simplify_gen_subreg (V4SImode, operands[1], V8HImode, 0); + subreg = simplify_gen_subreg (V4SImode, operands[1], <MODE>mode, 0); emit_insn (gen_vsx_ld_elemrev_v4si (tmp, subreg)); - subreg2 = simplify_gen_subreg (V8HImode, tmp, V4SImode, 0); + subreg2 = simplify_gen_subreg (<MODE>mode, tmp, V4SImode, 0); for (i = 0; i < 16; ++i) perm[i] = GEN_INT (reorder[i]); @@ -1462,21 +1487,21 @@ pcv = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm))); - emit_insn (gen_altivec_vperm_v8hi_direct (operands[0], subreg2, - subreg2, pcv)); + emit_insn (gen_altivec_vperm_<mode>_direct (operands[0], subreg2, + subreg2, pcv)); DONE; } }) -(define_insn "*vsx_ld_elemrev_v8hi_internal" - [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (vec_select:V8HI - (match_operand:V8HI 1 "memory_operand" "Z") +(define_insn "*vsx_ld_elemrev_<mode>_internal" + [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "memory_operand" "Z") (parallel [(const_int 7) (const_int 6) (const_int 5) (const_int 4) (const_int 3) (const_int 2) (const_int 1) (const_int 0)])))] - "VECTOR_MEM_VSX_P (V8HImode) && !BYTES_BIG_ENDIAN && TARGET_P9_VECTOR" + "VECTOR_MEM_VSX_P (<MODE>mode) && !BYTES_BIG_ENDIAN && TARGET_P9_VECTOR" "lxvh8x %x0,%y1" [(set_attr "type" "vecload")]) @@ -1584,20 +1609,20 @@ "stxvw4x %x1,%y0" [(set_attr "type" "vecstore")]) -(define_expand "vsx_st_elemrev_v8hi" - [(set (match_operand:V8HI 0 "memory_operand" "=Z") - (vec_select:V8HI - (match_operand:V8HI 1 "vsx_register_operand" "wa") +(define_expand "vsx_st_elemrev_<mode>" + [(set (match_operand:VECTOR_16BIT 0 "memory_operand" "=Z") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa") (parallel [(const_int 7) (const_int 6) (const_int 5) (const_int 4) (const_int 3) (const_int 2) (const_int 1) (const_int 0)])))] - "VECTOR_MEM_VSX_P (V8HImode) && !BYTES_BIG_ENDIAN" + "VECTOR_MEM_VSX_P (<MODE>mode) && !BYTES_BIG_ENDIAN" { if (!TARGET_P9_VECTOR) { rtx mem_subreg, subreg, perm[16], pcv; - rtx tmp = gen_reg_rtx (V8HImode); + rtx tmp = gen_reg_rtx (<MODE>mode); /* 2 is leftmost element in register */ unsigned int reorder[16] = {13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2}; int i; @@ -1608,10 +1633,10 @@ pcv = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm))); - emit_insn (gen_altivec_vperm_v8hi_direct (tmp, operands[1], - operands[1], pcv)); - subreg = simplify_gen_subreg (V4SImode, tmp, V8HImode, 0); - mem_subreg = simplify_gen_subreg (V4SImode, operands[0], V8HImode, 0); + emit_insn (gen_altivec_vperm_<mode>_direct (tmp, operands[1], + operands[1], pcv)); + subreg = simplify_gen_subreg (V4SImode, tmp, <MODE>mode, 0); + mem_subreg = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0); emit_insn (gen_vsx_st_elemrev_v4si (mem_subreg, subreg)); DONE; } @@ -1626,15 +1651,15 @@ "stxvd2x %x1,%y0" [(set_attr "type" "vecstore")]) -(define_insn "*vsx_st_elemrev_v8hi_internal" - [(set (match_operand:V8HI 0 "memory_operand" "=Z") - (vec_select:V8HI - (match_operand:V8HI 1 "vsx_register_operand" "wa") +(define_insn "*vsx_st_elemrev_<mode>_internal" + [(set (match_operand:VECTOR_16BIT 0 "memory_operand" "=Z") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa") (parallel [(const_int 7) (const_int 6) (const_int 5) (const_int 4) (const_int 3) (const_int 2) (const_int 1) (const_int 0)])))] - "VECTOR_MEM_VSX_P (V8HImode) && !BYTES_BIG_ENDIAN && TARGET_P9_VECTOR" + "VECTOR_MEM_VSX_P (<MODE>mode) && !BYTES_BIG_ENDIAN && TARGET_P9_VECTOR" "stxvh8x %x1,%y0" [(set_attr "type" "vecstore")]) @@ -3299,10 +3324,10 @@ "xxpermdi %x0,%x1,%x1,2" [(set_attr "type" "vecperm")]) -(define_insn "xxswapd_v8hi" - [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (vec_select:V8HI - (match_operand:V8HI 1 "vsx_register_operand" "wa") +(define_insn "xxswapd_<mode>" + [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) @@ -3402,15 +3427,15 @@ "lxvd2x %x0,%y1" [(set_attr "type" "vecload")]) -(define_insn "*vsx_lxvd2x8_le_V8HI" - [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (vec_select:V8HI - (match_operand:V8HI 1 "memory_operand" "Z") +(define_insn "*vsx_lxvd2x8_le_<MODE>" + [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "memory_operand" "Z") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode) && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" [(set_attr "type" "vecload")]) @@ -3478,15 +3503,15 @@ [(set_attr "type" "vecstore") (set_attr "length" "8")]) -(define_insn "*vsx_stxvd2x8_le_V8HI" - [(set (match_operand:V8HI 0 "memory_operand" "=Z") - (vec_select:V8HI - (match_operand:V8HI 1 "vsx_register_operand" "wa") +(define_insn "*vsx_stxvd2x8_le_<MODE>" + [(set (match_operand:VECTOR_16BIT 0 "memory_operand" "=Z") + (vec_select:VECTOR_16BIT + (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode) && !TARGET_P9_VECTOR" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0" [(set_attr "type" "vecstore")]) @@ -4060,7 +4085,8 @@ if (which_alternative == 0 && ((<MODE>mode == V16QImode && INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 7 : 8)) - || (<MODE>mode == V8HImode + || ((<MODE>mode == V8HImode || <MODE>mode == V8HFmode + || <MODE>mode == V8BFmode) && INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 3 : 4)))) { enum machine_mode dest_mode = GET_MODE (operands[0]); @@ -4139,7 +4165,8 @@ else vec_tmp = src; } - else if (<MODE>mode == V8HImode) + else if (<MODE>mode == V8HImode || <MODE>mode == V8HFmode + || <MODE>mode == V8BFmode) { if (value != 3) emit_insn (gen_altivec_vsplth_direct (vec_tmp, src, element));
