https://gcc.gnu.org/g:52ce3b923a0193ccaf4d57c4b2525290a607c46b
commit 52ce3b923a0193ccaf4d57c4b2525290a607c46b Author: Michael Meissner <[email protected]> Date: Sat Nov 8 05:13:31 2025 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index eb581d426b64..3df98f305e3d 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,3 +1,40 @@ +==================== Branch work224-dmf, patch #210 ==================== + +Use vector pair load/store for memcpy with -mcpu=future + +In the development for the power10 processor, GCC did not enable using the load +vector pair and store vector pair instructions when optimizing things like +memory copy. This patch enables using those instructions if -mcpu=future is +used. + +This patch assumes that the following previously posted patches have been +installed: + + * https://gcc.gnu.org/pipermail/gcc-patches/2025-November/699956.html + * https://gcc.gnu.org/pipermail/gcc-patches/2025-November/699977.html + * https://gcc.gnu.org/pipermail/gcc-patches/2025-November/699978.html + * https://gcc.gnu.org/pipermail/gcc-patches/2025-November/699979.html + +I have tested these patches on both big endian and little endian PowerPC +servers, with no regressions. Can I check these patchs into the trunk? + +2025-11-08 Michael Meissner <[email protected]> + +gcc/ + + * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Enable using load + vector pair and store vector pair instructions for memory copy + operations. + (POWERPC_MASKS): Make the option for enabling using load vector pair and + store vector pair operations set and reset when the PowerPC processor is + changed. + * gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable + -mblock-ops-vector-pair from influencing .machine selection. + +gcc/testsuite/ + + * gcc.target/powerpc/future-3.c: New test. + ==================== Branch work224-dmf, patch #202 ==================== Add support for 1,024 bit DMF registers.
