https://gcc.gnu.org/g:e57a5d065a7fda37efa122a04a7d32e09147f095
commit e57a5d065a7fda37efa122a04a7d32e09147f095 Author: Jeff Law <[email protected]> Date: Tue Nov 11 07:19:03 2025 -0700 [RISC-V] Improve detection of packw More infrastructure on the way to eliminating the define_insn_and_split for zero-extensions. Exposing the shift-pair approach in the expander may change the order in which operands appear in later RTL. In the case of packw detection order matters. It shouldn't, it's an IOR after all, but it does. So we should fix that. In addition to the ordering issue it slightly changes the form of one operand. So we want to handle that too. So there's a total of 3 new patterns. There isn't commonly available hardware with zbkb and it's only lightly tested in the testsuite. So I wouldn't be terribly surprised to find out there's other ways we want to represent those operands to ultimately generate a pack instruction. Built and tested on riscv32-elf and riscv64-elf in my tester. I'll wait for pre-commit CI to render a verdict before moving forward. gcc/ * config/riscv/crypto.md (packf splitters): Variant with operands reversed. Add variants with the ashift/sign extend exchanged as well. (cherry picked from commit 9d1294aeccd8623774b5ae5207874796caa84a59) Diff: --- gcc/config/riscv/crypto.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 37ab5c3ac5b4..98bb4d604122 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -173,6 +173,40 @@ (zero_extend:SI (match_dup 2)))))] "operands[1] = gen_lowpart (SImode, operands[1]);") +(define_split + [(set (match_operand:DI 0 "register_operand") + (ior:DI (zero_extend:DI (match_operand:HI 1 "register_operand")) + (ashift:DI + (sign_extend:DI (match_operand:HI 2 "register_operand")) + (const_int 16))))] + "TARGET_ZBKB && TARGET_64BIT" + [(set (match_dup 0) + (sign_extend:DI (ior:SI (ashift:SI (match_dup 2) (const_int 16)) + (zero_extend:SI (match_dup 1)))))] + "operands[2] = gen_lowpart (SImode, operands[2]);") + +(define_split + [(set (match_operand:DI 0 "register_operand") + (ior:DI (sign_extend:DI + (ashift:SI (match_operand:SI 1 "register_operand") + (const_int 16))) + (zero_extend:DI (match_operand:HI 2 "register_operand"))))] + "TARGET_ZBKB && TARGET_64BIT" + [(set (match_dup 0) + (sign_extend:DI (ior:SI (ashift:SI (match_dup 1) (const_int 16)) + (zero_extend:SI (match_dup 2)))))]) + +(define_split + [(set (match_operand:DI 0 "register_operand") + (ior:DI (zero_extend:DI (match_operand:HI 1 "register_operand")) + (sign_extend:DI + (ashift:SI (match_operand:SI 2 "register_operand") + (const_int 16)))))] + "TARGET_ZBKB && TARGET_64BIT" + [(set (match_dup 0) + (sign_extend:DI (ior:SI (ashift:SI (match_dup 2) (const_int 16)) + (zero_extend:SI (match_dup 1)))))]) + ;; And this patches the result of the splitter above. (define_insn "*riscv_packw_2" [(set (match_operand:DI 0 "register_operand" "=r")
