https://gcc.gnu.org/g:1c0897caa516bc564258266860e3b75054b9e78e
commit r16-5486-g1c0897caa516bc564258266860e3b75054b9e78e Author: Jakub Jelinek <[email protected]> Date: Fri Nov 21 14:06:05 2025 +0100 i386: Remove cond_{ashl,lshr,ashr}v{64,16,32}qi expanders [PR122598] As mentioned in the PR, the COND_SH{L,R} internal fns are expanded without fallback, their expansion must succeed, and furthermore they don't differentiate between scalar and vector shift counts, so again both have to be supported. That is the case of the {ashl,lshr,ashr}v*[hsd]i patterns which use nonimmediate_or_const_vec_dup_operand predicate for the shift count, so if the argument isn't const vec dup, it can be always legitimized by loading into a vector register. This is not the case of the QImode element conditional vector shifts, there is no fallback for those and we emit individual element shifts in that case when not conditional and shift count is not a constant. So, I'm afraid we can't announce such an expander because then the vectorizer etc. count with it being fully available. As I've tried to show in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122598#c9 even without this pattern we can sometimes emit vgf2p8affineqb $0, .LC0(%rip), %ymm0, %ymm0{%k1} etc. instructions. 2025-11-21 Jakub Jelinek <[email protected]> PR target/122598 * config/i386/predicates.md (const_vec_dup_operand): Remove. * config/i386/sse.md (cond<<insn><mode> with VI1_AVX512VL iterator): Remove. * gcc.target/i386/pr122598.c: New test. Diff: --- gcc/config/i386/predicates.md | 3 --- gcc/config/i386/sse.md | 18 ------------------ gcc/testsuite/gcc.target/i386/pr122598.c | 14 ++++++++++++++ 3 files changed, 14 insertions(+), 21 deletions(-) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 57950d318782..c468f5ad26e2 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1319,9 +1319,6 @@ (ior (match_operand 0 "nonimmediate_operand") (match_test "const_vec_duplicate_p (op)"))) -(define_predicate "const_vec_dup_operand" - (match_test "const_vec_duplicate_p (op)")) - ;; Return true when OP is either register operand, or any ;; CONST_VECTOR. (define_predicate "reg_or_const_vector_operand" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8b90845260a3..9a8d1767ec90 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -27293,24 +27293,6 @@ DONE; }) -(define_expand "cond_<insn><mode>" - [(set (match_operand:VI1_AVX512VL 0 "register_operand") - (vec_merge:VI1_AVX512VL - (any_shift:VI1_AVX512VL - (match_operand:VI1_AVX512VL 2 "register_operand") - (match_operand:VI1_AVX512VL 3 "const_vec_dup_operand")) - (match_operand:VI1_AVX512VL 4 "nonimm_or_0_operand") - (match_operand:<avx512fmaskmode> 1 "register_operand")))] - "TARGET_GFNI && TARGET_AVX512F" -{ - rtx count = XVECEXP (operands[3], 0, 0); - rtx matrix = ix86_vgf2p8affine_shift_matrix (operands[0], count, <CODE>); - emit_insn (gen_vgf2p8affineqb_<mode>_mask (operands[0], operands[2], matrix, - const0_rtx, operands[4], - operands[1])); - DONE; -}) - (define_expand "<insn><mode>3" [(set (match_operand:VI1_AVX512_3264 0 "register_operand") (any_rotate:VI1_AVX512_3264 diff --git a/gcc/testsuite/gcc.target/i386/pr122598.c b/gcc/testsuite/gcc.target/i386/pr122598.c new file mode 100644 index 000000000000..0b943b12a58f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr122598.c @@ -0,0 +1,14 @@ +/* PR target/122598 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mgfni" } */ + +typedef char V __attribute__ ((vector_size (64))); + +V +foo (V v) +{ + v >>= (V) {5}; + v -= ~0; + v += (V) {} < v; + return v; +}
