https://gcc.gnu.org/g:0591ab53005b31a0d780d683004d84a4633ac35f
commit r16-5818-g0591ab53005b31a0d780d683004d84a4633ac35f Author: David Guillen Fandos <[email protected]> Date: Fri Sep 19 18:48:10 2025 +0200 MIPS: Add WSBW instruction to perform bswapsi2 gcc/ChangeLog: * config/mips/mips.h (ISA_HAS_WSBW): Defined a new macro. * config/mips/mips.md (bswapsi2): Add new instruction. (wsbwsi2): Replace with expand to support both wsbw and wsbh. gcc/testsuite/ChangeLog: * gcc.target/mips/bswap-7.c: New test. Signed-off-by: David Guillen Fandos <[email protected]> Diff: --- gcc/config/mips/mips.h | 3 +++ gcc/config/mips/mips.md | 29 +++++++++++++++++++++-------- gcc/testsuite/gcc.target/mips/bswap-7.c | 9 +++++++++ 3 files changed, 33 insertions(+), 8 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a78f42148489..7d1fc6552d6f 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1263,6 +1263,9 @@ struct mips_cpu_info { #define ISA_HAS_WSBH ((mips_isa_rev >= 2 && !TARGET_MIPS16) \ || TARGET_ALLEGREX) +/* Similar to WSBH but for 32 bit words (byte swap within a word). */ +#define ISA_HAS_WSBW (TARGET_ALLEGREX) + /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || TARGET_LOONGSON_2EF \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d9aee8189596..939e51719297 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -6041,16 +6041,29 @@ "wsbh\t%0,%1" [(set_attr "type" "shift")]) -(define_insn_and_split "bswapsi2" +(define_expand "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "ISA_HAS_WSBW || (ISA_HAS_WSBH && ISA_HAS_ROR)" +{ + if (ISA_HAS_WSBW) { + emit_insn (gen_wsbwsi2 (operands[0], operands[1])); + } + else + { + rtx tmp = gen_reg_rtx (SImode); + emit_insn (gen_wsbh (tmp, operands[1])); + emit_insn (gen_rotrsi3 (operands[0], tmp, GEN_INT(16))); + } + DONE; +}) + +(define_insn "wsbwsi2" [(set (match_operand:SI 0 "register_operand" "=d") (bswap:SI (match_operand:SI 1 "register_operand" "d")))] - "ISA_HAS_WSBH && ISA_HAS_ROR" - "#" - "&& 1" - [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) - (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] - "" - [(set_attr "insn_count" "2")]) + "ISA_HAS_WSBW" + "wsbw\t%0,%1" + [(set_attr "type" "shift")]) (define_insn_and_split "bswapdi2" [(set (match_operand:DI 0 "register_operand" "=d") diff --git a/gcc/testsuite/gcc.target/mips/bswap-7.c b/gcc/testsuite/gcc.target/mips/bswap-7.c new file mode 100644 index 000000000000..c1f923eec021 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/bswap-7.c @@ -0,0 +1,9 @@ +/* { dg-options "-march=allegrex" } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +/* { dg-final { scan-assembler "\twsbw\t" } } */
