https://gcc.gnu.org/g:46c1b7d63b164df90d50334f8ac4090dbb17fac0
commit 46c1b7d63b164df90d50334f8ac4090dbb17fac0 Author: Michael Meissner <[email protected]> Date: Thu Dec 11 22:51:55 2025 -0500 Add -mbfloat16-vector for testing. 2025-12-11 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (xscvspdpn_sf): If -mbfloat16-vector, generate vector code, not scalar. (<fp16_vector8>_shift_left_32bit): Likewise. (<fp16_vector8>_shift_left_32bit_new): Likewise. (<fp16_vector8>_shift_left_32bit_orig): Likewise. * config/rs6000/rs6000.opt (-mbfloat16-vector): New debug option. Diff: --- gcc/config/rs6000/float16.md | 25 ++++++++++++++++++++++--- gcc/config/rs6000/rs6000.opt | 4 ++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index fe5422dc2892..0fb5e20300dd 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -281,17 +281,36 @@ (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" - "xscvspdpn %x0,%x1" +{ + return (TARGET_BFLOAT16_VECTOR + ? "xvcvspdp %x0,%x1" + : "xscvspdpn %x0,%x1"); +} [(set_attr "type" "fp")]) ;; Vector shift left by 32 bits to get the 16-bit floating point value ;; into the upper 32 bits for the conversion. -(define_insn "<fp16_vector8>_shift_left_32bit" +(define_expand "<fp16_vector8>_shift_left_32bit" + [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand") + (unspec:<FP16_VECTOR8> + [(match_operand:FP16_HW 1 "vsx_register_operand")] + UNSPEC_FP16_SHIFT_LEFT_32BIT))]) + +(define_insn "*<fp16_vector8>_shift_left_32bit_new" + [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=v") + (unspec:<FP16_VECTOR8> + [(match_operand:FP16_HW 1 "vsx_register_operand" "v")] + UNSPEC_FP16_SHIFT_LEFT_32BIT))] + "TARGET_BFLOAT16_VECTOR" + "vspltw %0,%1,1" + [(set_attr "type" "vecperm")]) + +(define_insn "*<fp16_vector8>_shift_left_32bit_orig" [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa") (unspec:<FP16_VECTOR8> [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] UNSPEC_FP16_SHIFT_LEFT_32BIT))] - "" + "!TARGET_BFLOAT16_VECTOR" "xxsldwi %x0,%x1,%x1,1" [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index c0fbe9bb2713..a392a63cdfc0 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -643,6 +643,10 @@ mfloat16 Target Mask(FLOAT16) Var(rs6000_isa_flags) Enable or disable 16-bit floating point. +mbfloat16-vector +Target Var(TARGET_BFLOAT16_VECTOR) Init(0) Save Undocumented +Change the code for bfloat16 conversions. + ; Documented parameters -param=rs6000-vect-unroll-limit=
