https://gcc.gnu.org/g:7bf897e7c4fabcade9dcdb80a23c2a0dc92cc063
commit r16-6393-g7bf897e7c4fabcade9dcdb80a23c2a0dc92cc063 Author: Sandra Loosemore <[email protected]> Date: Sun Dec 21 02:23:43 2025 +0000 doc, riscv: Clean up RISC-V extensions documentation This patch fixes a number of problems I observed in the RISC-V extensions documentation, which is autogenerated from .def files: - The formatting of the table looked terrible in the PDF output, with overlapping text. I made the first two columns wider to fix this. - Also the extension names in the table should have @samp{} markup. - Many extensions were missing a full name/description. (Documenting something as "xyzzy extension" adds nothing useful to readers when we are already listing the extension name "xyzzy" in the table.) - Irregular spelling and capitalization in the full names. gcc/ChangeLog * config/riscv/gen-riscv-ext-texi.cc: Fix table markup and layout. * config/riscv/riscv-ext-corev.def: Document missing extensions, regularize spelling/capitalization in existing descriptions * config/riscv/riscv-ext-mips.def: Likewise. * config/riscv/riscv-ext-sifive.def: Likewise. * config/riscv/riscv-ext-thead.def: Likewise. * config/riscv/riscv-ext.def: Likewise. * doc/riscv-ext.texi: Regenerated. Diff: --- gcc/config/riscv/gen-riscv-ext-texi.cc | 10 +- gcc/config/riscv/riscv-ext-corev.def | 4 +- gcc/config/riscv/riscv-ext-mips.def | 2 +- gcc/config/riscv/riscv-ext-sifive.def | 10 +- gcc/config/riscv/riscv-ext-thead.def | 2 +- gcc/config/riscv/riscv-ext.def | 94 +++---- gcc/doc/riscv-ext.texi | 476 ++++++++++++++++----------------- 7 files changed, 301 insertions(+), 297 deletions(-) diff --git a/gcc/config/riscv/gen-riscv-ext-texi.cc b/gcc/config/riscv/gen-riscv-ext-texi.cc index e0169910887b..53c8e9e01ced 100644 --- a/gcc/config/riscv/gen-riscv-ext-texi.cc +++ b/gcc/config/riscv/gen-riscv-ext-texi.cc @@ -35,7 +35,7 @@ print_ext_doc_entry (const std::string &ext_name, const std::string &full_name, std::set<version_t> unique_versions; for (const auto &version : supported_versions) unique_versions.insert (version); - printf ("@item %s\n", ext_name.c_str ()); + printf ("@item @samp{%s}\n", ext_name.c_str ()); printf ("@tab"); for (const auto &version : unique_versions) { @@ -62,15 +62,15 @@ main () puts (""); puts ("@c Please *DO NOT* edit manually."); puts (""); - puts ("@multitable @columnfractions .10 .10 .80"); + puts ("@multitable @columnfractions .25 .15 .6"); puts ("@headitem Extension Name @tab Supported Version @tab Description"); puts (""); - /* g extension is a very speical extension that no clear version... */ - puts ("@item g"); + /* g extension is a very special extension that has no clear version... */ + puts ("@item @samp{g}"); puts ("@tab -"); puts ( - "@tab General-purpose computing base extension, @samp{g} will expand to"); + "@tab General-purpose computing base extension; @samp{g} expands to"); puts ("@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and"); puts ("@samp{zifencei}."); puts (""); diff --git a/gcc/config/riscv/riscv-ext-corev.def b/gcc/config/riscv/riscv-ext-corev.def index c60a566eb61b..8012881b8cd1 100644 --- a/gcc/config/riscv/riscv-ext-corev.def +++ b/gcc/config/riscv/riscv-ext-corev.def @@ -37,7 +37,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xcvbi, /* UPPERCASE_NAME */ XCVBI, - /* FULL_NAME */ "xcvbi extension", + /* FULL_NAME */ "Core-V immediate branch extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -76,7 +76,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xcvsimd, /* UPPERCASE_NAME */ XCVSIMD, - /* FULL_NAME */ "xcvsimd extension", + /* FULL_NAME */ "Core-V SIMD extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), diff --git a/gcc/config/riscv/riscv-ext-mips.def b/gcc/config/riscv/riscv-ext-mips.def index 132f6c1060d5..8a83ac95dcaa 100644 --- a/gcc/config/riscv/riscv-ext-mips.def +++ b/gcc/config/riscv/riscv-ext-mips.def @@ -37,7 +37,7 @@ DEFINE_RISCV_EXT ( DEFINE_RISCV_EXT ( /* NAME. */ xmipscbop, /* UPPERCASE_NAME. */ XMIPSCBOP, - /* FULL_NAME. */ "Mips Prefetch extension", + /* FULL_NAME. */ "Mips prefetch extension", /* DESC. */ "", /* URL. */ , /* DEP_EXTS. */ ({}), diff --git a/gcc/config/riscv/riscv-ext-sifive.def b/gcc/config/riscv/riscv-ext-sifive.def index 26d4260914d0..3736b320e751 100644 --- a/gcc/config/riscv/riscv-ext-sifive.def +++ b/gcc/config/riscv/riscv-ext-sifive.def @@ -24,7 +24,7 @@ Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ DEFINE_RISCV_EXT( /* NAME */ xsfcease, /* UPPERCASE_NAME */ XSFCEASE, - /* FULL_NAME */ "xsfcease extension", + /* FULL_NAME */ "SiFive CEASE instruction extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -37,7 +37,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvcp, /* UPPERCASE_NAME */ XSFVCP, - /* FULL_NAME */ "xsfvcp extension", + /* FULL_NAME */ "SiFive VCIX vector coprocessor extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zve32x"}), @@ -50,7 +50,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvfnrclipxfqf, /* UPPERCASE_NAME */ XSFVFNRCLIPXFQF, - /* FULL_NAME */ "xsfvfnrclipxfqf extension", + /* FULL_NAME */ "SiFive FP32-to-int8 ranged clip instructions", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -63,7 +63,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvqmaccdod, /* UPPERCASE_NAME */ XSFVQMACCDOD, - /* FULL_NAME */ "xsfvqmaccdod extension", + /* FULL_NAME */ "SiFive int8 matrix multiplication extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -76,7 +76,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvqmaccqoq, /* UPPERCASE_NAME */ XSFVQMACCQOQ, - /* FULL_NAME */ "xsfvqmaccqoq extension", + /* FULL_NAME */ "SiFive int8 matrix multiplication extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), diff --git a/gcc/config/riscv/riscv-ext-thead.def b/gcc/config/riscv/riscv-ext-thead.def index c49bd0042035..65a3990286c4 100644 --- a/gcc/config/riscv/riscv-ext-thead.def +++ b/gcc/config/riscv/riscv-ext-thead.def @@ -180,7 +180,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadvector, /* UPPERCASE_NAME */ XTHEADVECTOR, - /* FULL_NAME */ "xtheadvector extension", + /* FULL_NAME */ "T-head vector extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index 62d638015f35..6130b5cd37e9 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -184,7 +184,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ b, /* UPPERCASE_NAME */ RVB, - /* FULL_NAME */ "b extension", + /* FULL_NAME */ "Standard extension for bit manipulation functions", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zba", "zbb", "zbs"}), @@ -223,7 +223,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zic64b, /* UPPERCASE_NAME */ ZIC64B, - /* FULL_NAME */ "Cache block size isf 64 bytes", + /* FULL_NAME */ "Cache block size is 64 bytes", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -327,7 +327,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zicfilp, /* UPPERCASE_NAME */ ZICFILP, - /* FULL_NAME */ "zicfilp extension", + /* FULL_NAME */ "Control-flow integrity landing pad extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -340,7 +340,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zicfiss, /* UPPERCASE_NAME */ ZICFISS, - /* FULL_NAME */ "zicfiss extension", + /* FULL_NAME */ "Control-flow integrity shadow stack extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr", "zimop"}), @@ -444,7 +444,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zimop, /* UPPERCASE_NAME */ ZIMOP, - /* FULL_NAME */ "zimop extension", + /* FULL_NAME */ "May-be-operations extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -457,7 +457,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zilsd, /* UPPERCASE_NAME */ ZILSD, - /* FULL_NAME */ "Load/Store pair instructions extension", + /* FULL_NAME */ "Load/store pair instructions extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -509,7 +509,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zaamo, /* UPPERCASE_NAME */ ZAAMO, - /* FULL_NAME */ "zaamo extension", + /* FULL_NAME */ "Atomic memory operations extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -522,7 +522,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zabha, /* UPPERCASE_NAME */ ZABHA, - /* FULL_NAME */ "zabha extension", + /* FULL_NAME */ "Byte and halfword atomic memory operations extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zaamo"}), @@ -535,7 +535,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zacas, /* UPPERCASE_NAME */ ZACAS, - /* FULL_NAME */ "zacas extension", + /* FULL_NAME */ "Atomic compare-and-swap instructions extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zaamo"}), @@ -548,7 +548,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zalrsc, /* UPPERCASE_NAME */ ZALRSC, - /* FULL_NAME */ "zalrsc extension", + /* FULL_NAME */ "Load-reserved/store-conditional subset of the A extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -574,9 +574,10 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zama16b, /* UPPERCASE_NAME */ ZAMA16B, - /* FULL_NAME */ "Zama16b extension", - /* DESC */ "Misaligned loads, stores, and AMOs to main memory regions that do" - " not cross a naturally aligned 16-byte boundary are atomic.", + /* FULL_NAME */ "Misaligned loads, stores, and AMOs that are fully" + " contained within a naturally-aligned 16-byte boundary" + " are atomic", + /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), /* SUPPORTED_VERSIONS */ ({{1, 0}}), @@ -601,7 +602,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zfbfmin, /* UPPERCASE_NAME */ ZFBFMIN, - /* FULL_NAME */ "zfbfmin extension", + /* FULL_NAME */ "Minimal BF16 support extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zfhmin"}), @@ -768,7 +769,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zcmop, /* UPPERCASE_NAME */ ZCMOP, - /* FULL_NAME */ "zcmop extension", + /* FULL_NAME */ "Compressed may-be-operations extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zca"}), @@ -1067,7 +1068,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvbc, /* UPPERCASE_NAME */ ZVBC, - /* FULL_NAME */ "Vector carryless multiplication extension", + /* FULL_NAME */ "Vector carry-less multiplication extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zve64x"}), @@ -1158,7 +1159,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvfbfwma, /* UPPERCASE_NAME */ ZVFBFWMA, - /* FULL_NAME */ "zvfbfwma extension", + /* FULL_NAME */ "Vector BF16 widening multiply/add extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvfbfmin", "zfbfmin"}), @@ -1236,7 +1237,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvknc, /* UPPERCASE_NAME */ ZVKNC, - /* FULL_NAME */ "Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc}", + /* FULL_NAME */ "Vector NIST Algorithm Suite with carry-less multiply extension, @samp{zvknc}", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvkn", "zvbc"}), @@ -1314,7 +1315,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvksc, /* UPPERCASE_NAME */ ZVKSC, - /* FULL_NAME */ "Vector ShangMi algorithm suite with carryless multiplication extension,", + /* FULL_NAME */ "Vector ShangMi algorithm suite with carry-less multiplication extension,", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvks", "zvbc"}), @@ -1327,7 +1328,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvksed, /* UPPERCASE_NAME */ ZVKSED, - /* FULL_NAME */ "Vector SM4 Block Cipher extension", + /* FULL_NAME */ "Vector SM4 block cipher extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zve32x"}), @@ -1340,7 +1341,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvksg, /* UPPERCASE_NAME */ ZVKSG, - /* FULL_NAME */ "Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand", + /* FULL_NAME */ "Vector ShangMi algorithm suite with GCM extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvks", "zvkg"}), @@ -1353,7 +1354,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvksh, /* UPPERCASE_NAME */ ZVKSH, - /* FULL_NAME */ "Vector SM3 Secure Hash extension", + /* FULL_NAME */ "Vector SM3 secure hash extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zve32x"}), @@ -1405,7 +1406,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvl16384b, /* UPPERCASE_NAME */ ZVL16384B, - /* FULL_NAME */ "zvl16384b extension", + /* FULL_NAME */ "Minimum vector length standard extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvl8192b"}), @@ -1444,7 +1445,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvl32768b, /* UPPERCASE_NAME */ ZVL32768B, - /* FULL_NAME */ "zvl32768b extension", + /* FULL_NAME */ "Minimum vector length standard extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvl16384b"}), @@ -1509,7 +1510,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvl65536b, /* UPPERCASE_NAME */ ZVL65536B, - /* FULL_NAME */ "zvl65536b extension", + /* FULL_NAME */ "Minimum vector length standard extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvl32768b"}), @@ -1522,7 +1523,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ zvl8192b, /* UPPERCASE_NAME */ ZVL8192B, - /* FULL_NAME */ "zvl8192b extension", + /* FULL_NAME */ "Minimum vector length standard extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zvl4096b"}), @@ -1561,7 +1562,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ sdtrig, /* UPPERCASE_NAME */ SDTRIG, - /* FULL_NAME */ "sdtrig extension", + /* FULL_NAME */ "Debug triggers extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1652,7 +1653,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ shvstvecd, /* UPPERCASE_NAME */ SHVSTVECD, - /* FULL_NAME */ "The vstvec register supports Direct mode", + /* FULL_NAME */ "The vstvec register supports direct mode", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"h"}), @@ -1704,7 +1705,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ smcsrind, /* UPPERCASE_NAME */ SMCSRIND, - /* FULL_NAME */ "Machine-Level Indirect CSR Access", + /* FULL_NAME */ "Machine-level indirect CSR access", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr", "sscsrind"}), @@ -1717,7 +1718,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ smepmp, /* UPPERCASE_NAME */ SMEPMP, - /* FULL_NAME */ "PMP Enhancements for memory access and execution prevention on Machine mode", + /* FULL_NAME */ "PMP enhancements for memory access and execution prevention on machine mode", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1730,7 +1731,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ smmpm, /* UPPERCASE_NAME */ SMMPM, - /* FULL_NAME */ "smmpm extension", + /* FULL_NAME */ "Supervisor-mode pointer masking extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1743,7 +1744,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ smnpm, /* UPPERCASE_NAME */ SMNPM, - /* FULL_NAME */ "smnpm extension", + /* FULL_NAME */ "Supervisor-mode pointer masking extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1782,7 +1783,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ smdbltrp, /* UPPERCASE_NAME */ SMDBLTRP, - /* FULL_NAME */ "Double Trap Extensions", + /* FULL_NAME */ "Double trap extensions", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1795,7 +1796,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ ssaia, /* UPPERCASE_NAME */ SSAIA, - /* FULL_NAME */ "Advanced interrupt architecture extension for supervisor-mode", + /* FULL_NAME */ "Advanced interrupt architecture extension for supervisor mode", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1821,7 +1822,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ sscofpmf, /* UPPERCASE_NAME */ SSCOFPMF, - /* FULL_NAME */ "Count overflow & filtering extension", + /* FULL_NAME */ "Count overflow and filtering extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1847,7 +1848,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ sscsrind, /* UPPERCASE_NAME */ SSCSRIND, - /* FULL_NAME */ "Supervisor-Level Indirect CSR Access", + /* FULL_NAME */ "Supervisor-mode indirect CSR access", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1860,7 +1861,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ ssnpm, /* UPPERCASE_NAME */ SSNPM, - /* FULL_NAME */ "ssnpm extension", + /* FULL_NAME */ "Supervisor-mode pointer masking extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1873,7 +1874,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ sspm, /* UPPERCASE_NAME */ SSPM, - /* FULL_NAME */ "sspm extension", + /* FULL_NAME */ "Supervisor-mode pointer masking extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -1886,7 +1887,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ ssstateen, /* UPPERCASE_NAME */ SSSTATEEN, - /* FULL_NAME */ "State-enable extension for supervisor-mode", + /* FULL_NAME */ "Supervisor-mode state-enable extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1925,7 +1926,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ sstvecd, /* UPPERCASE_NAME */ SSTVECD, - /* FULL_NAME */ "Stvec supports Direct mode", + /* FULL_NAME */ "Stvec supports direct mode", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1938,7 +1939,9 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ ssstrict, /* UPPERCASE_NAME */ SSSTRICT, - /* FULL_NAME */ "ssstrict extension", + /* FULL_NAME */ "Unimplemented reserved encodings raise illegal " + "instruction exceptions and no non-conforming extensions " + "are present", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1951,7 +1954,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ ssdbltrp, /* UPPERCASE_NAME */ SSDBLTRP, - /* FULL_NAME */ "Double Trap Extensions", + /* FULL_NAME */ "Double trap extensions", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), @@ -1977,7 +1980,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ supm, /* UPPERCASE_NAME */ SUPM, - /* FULL_NAME */ "supm extension", + /* FULL_NAME */ "User-mode pointer masking extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -2029,7 +2032,8 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ svvptc, /* UPPERCASE_NAME */ SVVPTC, - /* FULL_NAME */ "svvptc extension", + /* FULL_NAME */ "Extension for obviating memory-management instructions " + "after marking PTEs valid", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({}), @@ -2042,7 +2046,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ svadu, /* UPPERCASE_NAME */ SVADU, - /* FULL_NAME */ "Hardware Updating of A/D Bits extension", + /* FULL_NAME */ "Hardware updating of A/D bits extension", /* DESC */ "", /* URL */ , /* DEP_EXTS */ ({"zicsr"}), diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index 0dc667b561ca..278f0dcc5a4f 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -9,744 +9,744 @@ @c Please *DO NOT* edit manually. -@multitable @columnfractions .10 .10 .80 +@multitable @columnfractions .25 .15 .6 @headitem Extension Name @tab Supported Version @tab Description -@item g +@item @samp{g} @tab - -@tab General-purpose computing base extension, @samp{g} will expand to +@tab General-purpose computing base extension; @samp{g} expands to @samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and @samp{zifencei}. -@item e +@item @samp{e} @tab 2.0 @tab Reduced base integer extension -@item i +@item @samp{i} @tab 2.0 2.1 @tab Base integer extension -@item m +@item @samp{m} @tab 2.0 @tab Integer multiplication and division extension -@item a +@item @samp{a} @tab 2.0 2.1 @tab Atomic extension -@item f +@item @samp{f} @tab 2.0 2.2 @tab Single-precision floating-point extension -@item d +@item @samp{d} @tab 2.0 2.2 @tab Double-precision floating-point extension -@item c +@item @samp{c} @tab 2.0 @tab Compressed extension -@item b +@item @samp{b} @tab 1.0 -@tab b extension +@tab Standard extension for bit manipulation functions -@item v +@item @samp{v} @tab 1.0 @tab Vector extension -@item h +@item @samp{h} @tab 1.0 @tab Hypervisor extension -@item zic64b +@item @samp{zic64b} @tab 1.0 -@tab Cache block size isf 64 bytes +@tab Cache block size is 64 bytes -@item zicbom +@item @samp{zicbom} @tab 1.0 @tab Cache-block management extension -@item zicbop +@item @samp{zicbop} @tab 1.0 @tab Cache-block prefetch extension -@item zicboz +@item @samp{zicboz} @tab 1.0 @tab Cache-block zero extension -@item ziccamoa +@item @samp{ziccamoa} @tab 1.0 @tab Main memory supports all atomics in A -@item ziccif +@item @samp{ziccif} @tab 1.0 @tab Main memory supports instruction fetch with atomicity requirement -@item zicclsm +@item @samp{zicclsm} @tab 1.0 @tab Main memory supports misaligned loads/stores -@item ziccrse +@item @samp{ziccrse} @tab 1.0 @tab Main memory supports forward progress on LR/SC sequences -@item zicfilp +@item @samp{zicfilp} @tab 1.0 -@tab zicfilp extension +@tab Control-flow integrity landing pad extension -@item zicfiss +@item @samp{zicfiss} @tab 1.0 -@tab zicfiss extension +@tab Control-flow integrity shadow stack extension -@item zicntr +@item @samp{zicntr} @tab 2.0 @tab Standard extension for base counters and timers -@item zicond +@item @samp{zicond} @tab 1.0 @tab Integer conditional operations extension -@item zicsr +@item @samp{zicsr} @tab 2.0 @tab Control and status register access extension -@item zifencei +@item @samp{zifencei} @tab 2.0 @tab Instruction-fetch fence extension -@item zihintntl +@item @samp{zihintntl} @tab 1.0 @tab Non-temporal locality hints extension -@item zihintpause +@item @samp{zihintpause} @tab 2.0 @tab Pause hint extension -@item zihpm +@item @samp{zihpm} @tab 2.0 @tab Standard extension for hardware performance counters -@item zimop +@item @samp{zimop} @tab 1.0 -@tab zimop extension +@tab May-be-operations extension -@item zilsd +@item @samp{zilsd} @tab 1.0 -@tab Load/Store pair instructions extension +@tab Load/store pair instructions extension -@item zmmul +@item @samp{zmmul} @tab 1.0 @tab Integer multiplication extension -@item za128rs +@item @samp{za128rs} @tab 1.0 @tab Reservation set size of 128 bytes -@item za64rs +@item @samp{za64rs} @tab 1.0 @tab Reservation set size of 64 bytes -@item zaamo +@item @samp{zaamo} @tab 1.0 -@tab zaamo extension +@tab Atomic memory operations extension -@item zabha +@item @samp{zabha} @tab 1.0 -@tab zabha extension +@tab Byte and halfword atomic memory operations extension -@item zacas +@item @samp{zacas} @tab 1.0 -@tab zacas extension +@tab Atomic compare-and-swap instructions extension -@item zalrsc +@item @samp{zalrsc} @tab 1.0 -@tab zalrsc extension +@tab Load-reserved/store-conditional subset of the A extension -@item zawrs +@item @samp{zawrs} @tab 1.0 @tab Wait-on-reservation-set extension -@item zama16b +@item @samp{zama16b} @tab 1.0 -@tab Zama16b extension, Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. +@tab Misaligned loads, stores, and AMOs that are fully contained within a naturally-aligned 16-byte boundary are atomic -@item zfa +@item @samp{zfa} @tab 1.0 @tab Additional floating-point extension -@item zfbfmin +@item @samp{zfbfmin} @tab 1.0 -@tab zfbfmin extension +@tab Minimal BF16 support extension -@item zfh +@item @samp{zfh} @tab 1.0 @tab Half-precision floating-point extension -@item zfhmin +@item @samp{zfhmin} @tab 1.0 @tab Minimal half-precision floating-point extension -@item zfinx +@item @samp{zfinx} @tab 1.0 @tab Single-precision floating-point in integer registers extension -@item zdinx +@item @samp{zdinx} @tab 1.0 @tab Double-precision floating-point in integer registers extension -@item zca +@item @samp{zca} @tab 1.0 @tab Integer compressed instruction extension -@item zcb +@item @samp{zcb} @tab 1.0 @tab Simple compressed instruction extension -@item zcd +@item @samp{zcd} @tab 1.0 @tab Compressed double-precision floating point loads and stores extension -@item zce +@item @samp{zce} @tab 1.0 @tab Compressed instruction extensions for embedded processors -@item zcf +@item @samp{zcf} @tab 1.0 @tab Compressed single-precision floating point loads and stores extension -@item zcmop +@item @samp{zcmop} @tab 1.0 -@tab zcmop extension +@tab Compressed may-be-operations extension -@item zcmp +@item @samp{zcmp} @tab 1.0 @tab Compressed push pop extension -@item zcmt +@item @samp{zcmt} @tab 1.0 @tab Table jump instruction extension -@item zclsd +@item @samp{zclsd} @tab 1.0 @tab Compressed load/store pair instructions extension -@item zba +@item @samp{zba} @tab 1.0 @tab Address calculation extension -@item zbb +@item @samp{zbb} @tab 1.0 @tab Basic bit manipulation extension -@item zbc +@item @samp{zbc} @tab 1.0 @tab Carry-less multiplication extension -@item zbkb +@item @samp{zbkb} @tab 1.0 @tab Cryptography bit-manipulation extension -@item zbkc +@item @samp{zbkc} @tab 1.0 @tab Cryptography carry-less multiply extension -@item zbkx +@item @samp{zbkx} @tab 1.0 @tab Cryptography crossbar permutation extension -@item zbs +@item @samp{zbs} @tab 1.0 @tab Single-bit operation extension -@item zk +@item @samp{zk} @tab 1.0 @tab Standard scalar cryptography extension -@item zkn +@item @samp{zkn} @tab 1.0 @tab NIST algorithm suite extension -@item zknd +@item @samp{zknd} @tab 1.0 @tab AES Decryption extension -@item zkne +@item @samp{zkne} @tab 1.0 @tab AES Encryption extension -@item zknh +@item @samp{zknh} @tab 1.0 @tab Hash function extension -@item zkr +@item @samp{zkr} @tab 1.0 @tab Entropy source extension -@item zks +@item @samp{zks} @tab 1.0 @tab ShangMi algorithm suite extension -@item zksed +@item @samp{zksed} @tab 1.0 @tab SM4 block cipher extension -@item zksh +@item @samp{zksh} @tab 1.0 @tab SM3 hash function extension -@item zkt +@item @samp{zkt} @tab 1.0 @tab Data independent execution latency extension -@item ztso +@item @samp{ztso} @tab 1.0 @tab Total store ordering extension -@item zvbb +@item @samp{zvbb} @tab 1.0 @tab Vector basic bit-manipulation extension -@item zvbc +@item @samp{zvbc} @tab 1.0 -@tab Vector carryless multiplication extension +@tab Vector carry-less multiplication extension -@item zve32f +@item @samp{zve32f} @tab 1.0 @tab Vector extensions for embedded processors -@item zve32x +@item @samp{zve32x} @tab 1.0 @tab Vector extensions for embedded processors -@item zve64d +@item @samp{zve64d} @tab 1.0 @tab Vector extensions for embedded processors -@item zve64f +@item @samp{zve64f} @tab 1.0 @tab Vector extensions for embedded processors -@item zve64x +@item @samp{zve64x} @tab 1.0 @tab Vector extensions for embedded processors -@item zvfbfmin +@item @samp{zvfbfmin} @tab 1.0 @tab Vector BF16 converts extension -@item zvfbfwma +@item @samp{zvfbfwma} @tab 1.0 -@tab zvfbfwma extension +@tab Vector BF16 widening multiply/add extension -@item zvfh +@item @samp{zvfh} @tab 1.0 @tab Vector half-precision floating-point extension -@item zvfhmin +@item @samp{zvfhmin} @tab 1.0 @tab Vector minimal half-precision floating-point extension -@item zvkb +@item @samp{zvkb} @tab 1.0 @tab Vector cryptography bit-manipulation extension -@item zvkg +@item @samp{zvkg} @tab 1.0 @tab Vector GCM/GMAC extension -@item zvkn +@item @samp{zvkn} @tab 1.0 @tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to -@item zvknc +@item @samp{zvknc} @tab 1.0 -@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} +@tab Vector NIST Algorithm Suite with carry-less multiply extension, @samp{zvknc} -@item zvkned +@item @samp{zvkned} @tab 1.0 @tab Vector AES block cipher extension -@item zvkng +@item @samp{zvkng} @tab 1.0 @tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand -@item zvknha +@item @samp{zvknha} @tab 1.0 @tab Vector SHA-2 secure hash extension -@item zvknhb +@item @samp{zvknhb} @tab 1.0 @tab Vector SHA-2 secure hash extension -@item zvks +@item @samp{zvks} @tab 1.0 @tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand -@item zvksc +@item @samp{zvksc} @tab 1.0 -@tab Vector ShangMi algorithm suite with carryless multiplication extension, +@tab Vector ShangMi algorithm suite with carry-less multiplication extension, -@item zvksed +@item @samp{zvksed} @tab 1.0 -@tab Vector SM4 Block Cipher extension +@tab Vector SM4 block cipher extension -@item zvksg +@item @samp{zvksg} @tab 1.0 -@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand +@tab Vector ShangMi algorithm suite with GCM extension -@item zvksh +@item @samp{zvksh} @tab 1.0 -@tab Vector SM3 Secure Hash extension +@tab Vector SM3 secure hash extension -@item zvkt +@item @samp{zvkt} @tab 1.0 @tab Vector data independent execution latency extension -@item zvl1024b +@item @samp{zvl1024b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl128b +@item @samp{zvl128b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl16384b +@item @samp{zvl16384b} @tab 1.0 -@tab zvl16384b extension +@tab Minimum vector length standard extension -@item zvl2048b +@item @samp{zvl2048b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl256b +@item @samp{zvl256b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl32768b +@item @samp{zvl32768b} @tab 1.0 -@tab zvl32768b extension +@tab Minimum vector length standard extension -@item zvl32b +@item @samp{zvl32b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl4096b +@item @samp{zvl4096b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl512b +@item @samp{zvl512b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl64b +@item @samp{zvl64b} @tab 1.0 @tab Minimum vector length standard extensions -@item zvl65536b +@item @samp{zvl65536b} @tab 1.0 -@tab zvl65536b extension +@tab Minimum vector length standard extension -@item zvl8192b +@item @samp{zvl8192b} @tab 1.0 -@tab zvl8192b extension +@tab Minimum vector length standard extension -@item zhinx +@item @samp{zhinx} @tab 1.0 @tab Half-precision floating-point in integer registers extension -@item zhinxmin +@item @samp{zhinxmin} @tab 1.0 @tab Minimal half-precision floating-point in integer registers extension -@item sdtrig +@item @samp{sdtrig} @tab 1.0 -@tab sdtrig extension +@tab Debug triggers extension -@item sha +@item @samp{sha} @tab 1.0 @tab The augmented hypervisor extension -@item shcounterenw +@item @samp{shcounterenw} @tab 1.0 @tab Support writeable enables for any supported counter -@item shgatpa +@item @samp{shgatpa} @tab 1.0 @tab SvNNx4 mode supported for all modes supported by satp -@item shlcofideleg +@item @samp{shlcofideleg} @tab 1.0 @tab Delegating LCOFI interrupts to VS-mode -@item shtvala +@item @samp{shtvala} @tab 1.0 @tab The htval register provides all needed values -@item shvstvala +@item @samp{shvstvala} @tab 1.0 @tab The vstval register provides all needed values -@item shvstvecd +@item @samp{shvstvecd} @tab 1.0 -@tab The vstvec register supports Direct mode +@tab The vstvec register supports direct mode -@item shvsatpa +@item @samp{shvsatpa} @tab 1.0 @tab The vsatp register supports all modes supported by satp -@item smaia +@item @samp{smaia} @tab 1.0 @tab Advanced interrupt architecture extension -@item smcntrpmf +@item @samp{smcntrpmf} @tab 1.0 @tab Cycle and instret privilege mode filtering -@item smcsrind +@item @samp{smcsrind} @tab 1.0 -@tab Machine-Level Indirect CSR Access +@tab Machine-level indirect CSR access -@item smepmp +@item @samp{smepmp} @tab 1.0 -@tab PMP Enhancements for memory access and execution prevention on Machine mode +@tab PMP enhancements for memory access and execution prevention on machine mode -@item smmpm +@item @samp{smmpm} @tab 1.0 -@tab smmpm extension +@tab Supervisor-mode pointer masking extension -@item smnpm +@item @samp{smnpm} @tab 1.0 -@tab smnpm extension +@tab Supervisor-mode pointer masking extension -@item smrnmi +@item @samp{smrnmi} @tab 1.0 @tab Resumable non-maskable interrupts -@item smstateen +@item @samp{smstateen} @tab 1.0 @tab State enable extension -@item smdbltrp +@item @samp{smdbltrp} @tab 1.0 -@tab Double Trap Extensions +@tab Double trap extensions -@item ssaia +@item @samp{ssaia} @tab 1.0 -@tab Advanced interrupt architecture extension for supervisor-mode +@tab Advanced interrupt architecture extension for supervisor mode -@item ssccptr +@item @samp{ssccptr} @tab 1.0 @tab Main memory supports page table reads -@item sscofpmf +@item @samp{sscofpmf} @tab 1.0 -@tab Count overflow & filtering extension +@tab Count overflow and filtering extension -@item sscounterenw +@item @samp{sscounterenw} @tab 1.0 @tab Support writeable enables for any supported counter -@item sscsrind +@item @samp{sscsrind} @tab 1.0 -@tab Supervisor-Level Indirect CSR Access +@tab Supervisor-mode indirect CSR access -@item ssnpm +@item @samp{ssnpm} @tab 1.0 -@tab ssnpm extension +@tab Supervisor-mode pointer masking extension -@item sspm +@item @samp{sspm} @tab 1.0 -@tab sspm extension +@tab Supervisor-mode pointer masking extension -@item ssstateen +@item @samp{ssstateen} @tab 1.0 -@tab State-enable extension for supervisor-mode +@tab Supervisor-mode state-enable extension -@item sstc +@item @samp{sstc} @tab 1.0 @tab Supervisor-mode timer interrupts extension -@item sstvala +@item @samp{sstvala} @tab 1.0 @tab Stval provides all needed values -@item sstvecd +@item @samp{sstvecd} @tab 1.0 -@tab Stvec supports Direct mode +@tab Stvec supports direct mode -@item ssstrict +@item @samp{ssstrict} @tab 1.0 -@tab ssstrict extension +@tab Unimplemented reserved encodings raise illegal instruction exceptions and no non-conforming extensions are present -@item ssdbltrp +@item @samp{ssdbltrp} @tab 1.0 -@tab Double Trap Extensions +@tab Double trap extensions -@item ssu64xl +@item @samp{ssu64xl} @tab 1.0 @tab UXLEN=64 must be supported -@item supm +@item @samp{supm} @tab 1.0 -@tab supm extension +@tab User-mode pointer masking extension -@item svinval +@item @samp{svinval} @tab 1.0 @tab Fine-grained address-translation cache invalidation extension -@item svnapot +@item @samp{svnapot} @tab 1.0 @tab NAPOT translation contiguity extension -@item svpbmt +@item @samp{svpbmt} @tab 1.0 @tab Page-based memory types extension -@item svvptc +@item @samp{svvptc} @tab 1.0 -@tab svvptc extension +@tab Extension for obviating memory-management instructions after marking PTEs valid -@item svadu +@item @samp{svadu} @tab 1.0 -@tab Hardware Updating of A/D Bits extension +@tab Hardware updating of A/D bits extension -@item svade +@item @samp{svade} @tab 1.0 @tab Cause exception when hardware updating of A/D bits is disabled -@item svbare +@item @samp{svbare} @tab 1.0 @tab Satp mode bare is supported -@item xcvalu +@item @samp{xcvalu} @tab 1.0 @tab Core-V miscellaneous ALU extension -@item xcvbi +@item @samp{xcvbi} @tab 1.0 -@tab xcvbi extension +@tab Core-V immediate branch extension -@item xcvelw +@item @samp{xcvelw} @tab 1.0 @tab Core-V event load word extension -@item xcvmac +@item @samp{xcvmac} @tab 1.0 @tab Core-V multiply-accumulate extension -@item xcvsimd +@item @samp{xcvsimd} @tab 1.0 -@tab xcvsimd extension +@tab Core-V SIMD extension -@item xsfcease +@item @samp{xsfcease} @tab 1.0 -@tab xsfcease extension +@tab SiFive CEASE instruction extension -@item xsfvcp +@item @samp{xsfvcp} @tab 1.0 -@tab xsfvcp extension +@tab SiFive VCIX vector coprocessor extension -@item xsfvfnrclipxfqf +@item @samp{xsfvfnrclipxfqf} @tab 1.0 -@tab xsfvfnrclipxfqf extension +@tab SiFive FP32-to-int8 ranged clip instructions -@item xsfvqmaccdod +@item @samp{xsfvqmaccdod} @tab 1.0 -@tab xsfvqmaccdod extension +@tab SiFive int8 matrix multiplication extension -@item xsfvqmaccqoq +@item @samp{xsfvqmaccqoq} @tab 1.0 -@tab xsfvqmaccqoq extension +@tab SiFive int8 matrix multiplication extension -@item xtheadba +@item @samp{xtheadba} @tab 1.0 @tab T-head address calculation extension -@item xtheadbb +@item @samp{xtheadbb} @tab 1.0 @tab T-head basic bit-manipulation extension -@item xtheadbs +@item @samp{xtheadbs} @tab 1.0 @tab T-head single-bit instructions extension -@item xtheadcmo +@item @samp{xtheadcmo} @tab 1.0 @tab T-head cache management operations extension -@item xtheadcondmov +@item @samp{xtheadcondmov} @tab 1.0 @tab T-head conditional move extension -@item xtheadfmemidx +@item @samp{xtheadfmemidx} @tab 1.0 @tab T-head indexed memory operations for floating-point registers extension -@item xtheadfmv +@item @samp{xtheadfmv} @tab 1.0 @tab T-head double floating-point high-bit data transmission extension -@item xtheadint +@item @samp{xtheadint} @tab 1.0 @tab T-head acceleration interruption extension -@item xtheadmac +@item @samp{xtheadmac} @tab 1.0 @tab T-head multiply-accumulate extension -@item xtheadmemidx +@item @samp{xtheadmemidx} @tab 1.0 @tab T-head indexed memory operation extension -@item xtheadmempair +@item @samp{xtheadmempair} @tab 1.0 @tab T-head two-GPR memory operation extension -@item xtheadsync +@item @samp{xtheadsync} @tab 1.0 @tab T-head multi-core synchronization extension -@item xtheadvector +@item @samp{xtheadvector} @tab 1.0 -@tab xtheadvector extension +@tab T-head vector extension -@item xventanacondops +@item @samp{xventanacondops} @tab 1.0 @tab Ventana integer conditional operations extension -@item xmipscmov +@item @samp{xmipscmov} @tab 1.0 @tab Mips conditional move extension -@item xmipscbop +@item @samp{xmipscbop} @tab 1.0 -@tab Mips Prefetch extension +@tab Mips prefetch extension -@item xandesperf +@item @samp{xandesperf} @tab 5.0 @tab Andes performace extension -@item xandesbfhcvt +@item @samp{xandesbfhcvt} @tab 5.0 @tab Andes bfloat16 conversion extension -@item xandesvbfhcvt +@item @samp{xandesvbfhcvt} @tab 5.0 @tab Andes vector bfloat16 conversion extension -@item xandesvsintload +@item @samp{xandesvsintload} @tab 5.0 @tab Andes vector INT4 load extension -@item xandesvpackfph +@item @samp{xandesvpackfph} @tab 5.0 @tab Andes vector packed FP16 extension -@item xandesvdot +@item @samp{xandesvdot} @tab 5.0 @tab Andes vector dot product extension -@item xsmtvdot +@item @samp{xsmtvdot} @tab 1.0 @tab SpacemiT vector dot product extension
