https://gcc.gnu.org/g:699d4562eaa14130de65fd468181b78428d4f7f0
commit r16-6804-g699d4562eaa14130de65fd468181b78428d4f7f0 Author: Alfie Richards <[email protected]> Date: Fri Jan 9 16:51:34 2026 +0000 aarch64: Add comment explaining code layout gcc/ChangeLog: * config/aarch64/aarch64-simd.md: Add comment. * config/aarch64/aarch64-sme.md: Likewise. * config/aarch64/aarch64-sve-builtins-base.def: Likewise. * config/aarch64/aarch64-sve-builtins-sme.def: Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. * config/aarch64/aarch64-sve-builtins.def: Likewise. * config/aarch64/aarch64-sve.md: Likewise. * config/aarch64/aarch64-sve2.md: Likewise. * config/aarch64/aarch64.md: Likewise. Diff: --- gcc/config/aarch64/aarch64-simd.md | 18 ++++++++++++++++++ gcc/config/aarch64/aarch64-sme.md | 18 ++++++++++++++++++ gcc/config/aarch64/aarch64-sve-builtins-base.def | 17 +++++++++++++++++ gcc/config/aarch64/aarch64-sve-builtins-sme.def | 16 ++++++++++++++++ gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 17 +++++++++++++++++ gcc/config/aarch64/aarch64-sve-builtins.def | 17 +++++++++++++++++ gcc/config/aarch64/aarch64-sve.md | 18 ++++++++++++++++++ gcc/config/aarch64/aarch64-sve2.md | 18 ++++++++++++++++++ gcc/config/aarch64/aarch64.md | 18 ++++++++++++++++++ 9 files changed, 157 insertions(+) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a007cfe9abbf..7a38310efce8 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -18,6 +18,24 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +;; Code organisation: +; +;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are +;; a little blurry. +;; +;; Therefore code is organised by the following rough principles: +;; +;; - aarch64.md: For shared parts of the architecture (such as defining +;; registers and constants) and for instructions that operate on non-SIMD +;; registers. +;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD +;; registers. +;; - aarch64-sve.md for SVE instructions that are pre SVE2. +;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with +;; non-streaming mode. This usually means it uses the ZA or ZT register. +;; - aarch64-sve2.md for any scalable SIMD instruction that either is +;; streaming compatible, or theoretically could be later. + ;; The following define_subst rules are used to produce patterns representing ;; the implicit zeroing effect of 64-bit Advanced SIMD operations, in effect ;; a vec_concat with zeroes. The order of the vec_concat operands differs diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md index ca3ed4716570..a2faa4b2bb73 100644 --- a/gcc/config/aarch64/aarch64-sme.md +++ b/gcc/config/aarch64/aarch64-sme.md @@ -17,6 +17,24 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +;; Code organisation: +; +;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are +;; a little blurry. +;; +;; Therefore code is organised by the following rough principles: +;; +;; - aarch64.md: For shared parts of the architecture (such as defining +;; registers and constants) and for instructions that operate on non-SIMD +;; registers. +;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD +;; registers. +;; - aarch64-sve.md for SVE instructions that are pre SVE2. +;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with +;; non-streaming mode. This usually means it uses the ZA or ZT register. +;; - aarch64-sve2.md for any scalable SIMD instruction that either is +;; streaming compatible, or theoretically could be later. + ;; The file is organised into the following sections (search for the full ;; line): ;; diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.def b/gcc/config/aarch64/aarch64-sve-builtins-base.def index 3ffee71d31b8..0a3a7a0e144e 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.def @@ -17,6 +17,23 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* Code organisation: + + The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get + a little blurry. + + Therefore code is organised by the following rough principles: + + - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally + incompatible with non-streaming mode. This usually means it uses the ZA + or ZT register. + - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode + intrinsic, but either is non-streaming compatible, or theoretically could + be later. + - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. + - aarch64-sve-builtins.def for common data types and group definitions used + across all files. */ + #define REQUIRED_EXTENSIONS ssve (0) DEF_SVE_FUNCTION (svabd, binary_opt_n, all_arith, mxz) DEF_SVE_FUNCTION (svabs, unary, all_float_and_signed, mxz) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def index 1c9098348359..9f126e8647a2 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def @@ -17,6 +17,22 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* Code organisation: + + The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get + a little blurry. + + Therefore code is organised by the following rough principles: + + - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally + incompatible with non-streaming mode. This usually means it uses the ZA + or ZT register. + - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode + intrinsic, but either is non-streaming compatible, or theoretically could + be later. + - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. + - aarch64-sve-builtins.def for common data types and group definitions used + across all files. */ #ifndef DEF_SME_FUNCTION_GS #define DEF_SME_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \ diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index 9329c8853864..8765021d951f 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -17,6 +17,23 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* Code organisation: + + The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get + a little blurry. + + Therefore code is organised by the following rough principles: + + - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally + incompatible with non-streaming mode. This usually means it uses the ZA + or ZT register. + - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode + intrinsic, but either is non-streaming compatible, or theoretically could + be later. + - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. + - aarch64-sve-builtins.def for common data types and group definitions used + across all files. */ + #define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2, 0) DEF_SVE_FUNCTION (svaba, ternary_opt_n, all_integer, none) DEF_SVE_FUNCTION (svabalb, ternary_long_opt_n, hsd_integer, none) diff --git a/gcc/config/aarch64/aarch64-sve-builtins.def b/gcc/config/aarch64/aarch64-sve-builtins.def index ecdb77c3b157..ecd434bda35e 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.def +++ b/gcc/config/aarch64/aarch64-sve-builtins.def @@ -17,6 +17,23 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* Code organisation: + + The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get + a little blurry. + + Therefore code is organised by the following rough principles: + + - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally + incompatible with non-streaming mode. This usually means it uses the ZA + or ZT register. + - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode + intrinsic, but either is non-streaming compatible, or theoretically could + be later. + - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. + - aarch64-sve-builtins.def for common data types and group definitions used + across all files. */ + #ifndef DEF_SVE_MODE #define DEF_SVE_MODE(A, B, C, D) #endif diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index cc024a81746a..b77a04cd2d2d 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -18,6 +18,24 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +;; Code organisation: +; +;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are +;; a little blurry. +;; +;; Therefore code is organised by the following rough principles: +;; +;; - aarch64.md: For shared parts of the architecture (such as defining +;; registers and constants) and for instructions that operate on non-SIMD +;; registers. +;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD +;; registers. +;; - aarch64-sve.md for SVE instructions that are pre SVE2. +;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with +;; non-streaming mode. This usually means it uses the ZA or ZT register. +;; - aarch64-sve2.md for any scalable SIMD instruction that either is +;; streaming compatible, or theoretically could be later. + ;; The file is organised into the following sections (search for the full ;; line): ;; diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 2df93a4ba4cd..f959837eca0a 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -17,6 +17,24 @@ ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +; +;; Code organisation: +; +;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are +;; a little blurry. +;; +;; Therefore code is organised by the following rough principles: +;; +;; - aarch64.md: For shared parts of the architecture (such as defining +;; registers and constants) and for instructions that operate on non-SIMD +;; registers. +;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD +;; registers. +;; - aarch64-sve.md for SVE instructions that are pre SVE2. +;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with +;; non-streaming mode. This usually means it uses the ZA or ZT register. +;; - aarch64-sve2.md for any scalable SIMD instruction that either is +;; streaming compatible, or theoretically could be later. ;; The file is organised into the following sections (search for the full ;; line): diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4445208bf92c..58e57fd65a79 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -18,6 +18,24 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +;; Code organisation: +; +;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are +;; a little blurry. +;; +;; Therefore code is organised by the following rough principles: +;; +;; - aarch64.md: For shared parts of the architecture (such as defining +;; registers and constants) and for instructions that operate on non-SIMD +;; registers. +;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD +;; registers. +;; - aarch64-sve.md for SVE instructions that are pre SVE2. +;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with +;; non-streaming mode. This usually means it uses the ZA or ZT register. +;; - aarch64-sve2.md for any scalable SIMD instruction that either is +;; streaming compatible, or theoretically could be later. + ;; Register numbers (define_constants [
